Loading drivers/dma/idma64.c +8 −14 Original line number Diff line number Diff line Loading @@ -178,20 +178,12 @@ static irqreturn_t idma64_irq(int irq, void *dev) if (!status) return IRQ_NONE; /* Disable interrupts */ channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask); channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask); status_xfer = dma_readl(idma64, RAW(XFER)); status_err = dma_readl(idma64, RAW(ERROR)); for (i = 0; i < idma64->dma.chancnt; i++) idma64_chan_irq(idma64, i, status_err, status_xfer); /* Re-enable interrupts */ channel_set_bit(idma64, MASK(XFER), idma64->all_chan_mask); channel_set_bit(idma64, MASK(ERROR), idma64->all_chan_mask); return IRQ_HANDLED; } Loading Loading @@ -239,7 +231,7 @@ static void idma64_vdesc_free(struct virt_dma_desc *vdesc) idma64_desc_free(idma64c, to_idma64_desc(vdesc)); } static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw, static void idma64_hw_desc_fill(struct idma64_hw_desc *hw, struct dma_slave_config *config, enum dma_transfer_direction direction, u64 llp) { Loading Loading @@ -276,26 +268,26 @@ static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw, IDMA64C_CTLL_SRC_WIDTH(src_width); lli->llp = llp; return hw->llp; } static void idma64_desc_fill(struct idma64_chan *idma64c, struct idma64_desc *desc) { struct dma_slave_config *config = &idma64c->config; struct idma64_hw_desc *hw = &desc->hw[desc->ndesc - 1]; unsigned int i = desc->ndesc; struct idma64_hw_desc *hw = &desc->hw[i - 1]; struct idma64_lli *lli = hw->lli; u64 llp = 0; unsigned int i = desc->ndesc; /* Fill the hardware descriptors and link them to a list */ do { hw = &desc->hw[--i]; llp = idma64_hw_desc_fill(hw, config, desc->direction, llp); idma64_hw_desc_fill(hw, config, desc->direction, llp); llp = hw->llp; desc->length += hw->len; } while (i); /* Trigger interrupt after last block */ /* Trigger an interrupt after the last block is transfered */ lli->ctllo |= IDMA64C_CTLL_INT_EN; } Loading Loading @@ -596,6 +588,8 @@ static int idma64_probe(struct idma64_chip *chip) idma64->dma.dev = chip->dev; dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK); ret = dma_async_device_register(&idma64->dma); if (ret) return ret; Loading drivers/dma/idma64.h +2 −1 Original line number Diff line number Diff line Loading @@ -54,7 +54,8 @@ #define IDMA64C_CTLL_LLP_S_EN (1 << 28) /* src block chain */ /* Bitfields in CTL_HI */ #define IDMA64C_CTLH_BLOCK_TS(x) ((x) & ((1 << 17) - 1)) #define IDMA64C_CTLH_BLOCK_TS_MASK ((1 << 17) - 1) #define IDMA64C_CTLH_BLOCK_TS(x) ((x) & IDMA64C_CTLH_BLOCK_TS_MASK) #define IDMA64C_CTLH_DONE (1 << 17) /* Bitfields in CFG_LO */ Loading Loading
drivers/dma/idma64.c +8 −14 Original line number Diff line number Diff line Loading @@ -178,20 +178,12 @@ static irqreturn_t idma64_irq(int irq, void *dev) if (!status) return IRQ_NONE; /* Disable interrupts */ channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask); channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask); status_xfer = dma_readl(idma64, RAW(XFER)); status_err = dma_readl(idma64, RAW(ERROR)); for (i = 0; i < idma64->dma.chancnt; i++) idma64_chan_irq(idma64, i, status_err, status_xfer); /* Re-enable interrupts */ channel_set_bit(idma64, MASK(XFER), idma64->all_chan_mask); channel_set_bit(idma64, MASK(ERROR), idma64->all_chan_mask); return IRQ_HANDLED; } Loading Loading @@ -239,7 +231,7 @@ static void idma64_vdesc_free(struct virt_dma_desc *vdesc) idma64_desc_free(idma64c, to_idma64_desc(vdesc)); } static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw, static void idma64_hw_desc_fill(struct idma64_hw_desc *hw, struct dma_slave_config *config, enum dma_transfer_direction direction, u64 llp) { Loading Loading @@ -276,26 +268,26 @@ static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw, IDMA64C_CTLL_SRC_WIDTH(src_width); lli->llp = llp; return hw->llp; } static void idma64_desc_fill(struct idma64_chan *idma64c, struct idma64_desc *desc) { struct dma_slave_config *config = &idma64c->config; struct idma64_hw_desc *hw = &desc->hw[desc->ndesc - 1]; unsigned int i = desc->ndesc; struct idma64_hw_desc *hw = &desc->hw[i - 1]; struct idma64_lli *lli = hw->lli; u64 llp = 0; unsigned int i = desc->ndesc; /* Fill the hardware descriptors and link them to a list */ do { hw = &desc->hw[--i]; llp = idma64_hw_desc_fill(hw, config, desc->direction, llp); idma64_hw_desc_fill(hw, config, desc->direction, llp); llp = hw->llp; desc->length += hw->len; } while (i); /* Trigger interrupt after last block */ /* Trigger an interrupt after the last block is transfered */ lli->ctllo |= IDMA64C_CTLL_INT_EN; } Loading Loading @@ -596,6 +588,8 @@ static int idma64_probe(struct idma64_chip *chip) idma64->dma.dev = chip->dev; dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK); ret = dma_async_device_register(&idma64->dma); if (ret) return ret; Loading
drivers/dma/idma64.h +2 −1 Original line number Diff line number Diff line Loading @@ -54,7 +54,8 @@ #define IDMA64C_CTLL_LLP_S_EN (1 << 28) /* src block chain */ /* Bitfields in CTL_HI */ #define IDMA64C_CTLH_BLOCK_TS(x) ((x) & ((1 << 17) - 1)) #define IDMA64C_CTLH_BLOCK_TS_MASK ((1 << 17) - 1) #define IDMA64C_CTLH_BLOCK_TS(x) ((x) & IDMA64C_CTLH_BLOCK_TS_MASK) #define IDMA64C_CTLH_DONE (1 << 17) /* Bitfields in CFG_LO */ Loading