Loading Documentation/devicetree/bindings/arm/coresight.txt +3 −0 Original line number Diff line number Diff line Loading @@ -110,6 +110,9 @@ its hardware characteristcs. * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the source is considered to belong to CPU0. * qcom,tupwr-disable: For ETM, don't keep trace unit powered across power collapse. * Optional property for TMC: * arm,buffer-size: size of contiguous buffer space for TMC ETR Loading arch/arm64/boot/dts/qcom/msm8937-coresight.dtsi +16 −0 Original line number Diff line number Diff line Loading @@ -462,6 +462,8 @@ reg = <0x619c000 0x1000>; cpu = <&CPU4>; qcom,tupwr-disable; coresight-name = "coresight-etm4"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -481,6 +483,8 @@ reg = <0x619d000 0x1000>; cpu = <&CPU5>; qcom,tupwr-disable; coresight-name = "coresight-etm5"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -500,6 +504,8 @@ reg = <0x619e000 0x1000>; cpu = <&CPU6>; qcom,tupwr-disable; coresight-name = "coresight-etm6"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -519,6 +525,8 @@ reg = <0x619f000 0x1000>; cpu = <&CPU7>; qcom,tupwr-disable; coresight-name = "coresight-etm7"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -538,6 +546,8 @@ reg = <0x61bc000 0x1000>; cpu = <&CPU0>; qcom,tupwr-disable; coresight-name = "coresight-etm0"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -557,6 +567,8 @@ reg = <0x61bd000 0x1000>; cpu = <&CPU1>; qcom,tupwr-disable; coresight-name = "coresight-etm1"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -576,6 +588,8 @@ reg = <0x61be000 0x1000>; cpu = <&CPU2>; qcom,tupwr-disable; coresight-name = "coresight-etm2"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -594,6 +608,8 @@ arm,primecell-periphid = <0x000bb95d>; reg = <0x61bf000 0x1000>; qcom,tupwr-disable; coresight-name = "coresight-etm3"; cpu = <&CPU3>; Loading arch/arm64/boot/dts/qcom/msm8953-coresight.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -505,6 +505,8 @@ reg = <0x619c000 0x1000>; cpu = <&CPU0>; qcom,tupwr-disable; coresight-name = "coresight-etm0"; clocks = <&clock_gcc clk_qdss_clk>, Loading drivers/hwtracing/coresight/coresight-etm4x.c +18 −10 Original line number Diff line number Diff line Loading @@ -27,6 +27,7 @@ #include <linux/cpu.h> #include <linux/coresight.h> #include <linux/coresight-pmu.h> #include <linux/of.h> #include <linux/pm_wakeup.h> #include <linux/amba/bus.h> #include <linux/seq_file.h> Loading Loading @@ -167,12 +168,14 @@ static void etm4_enable_hw(void *info) writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0); writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1); if (!drvdata->tupwr_disable) { /* * Request to keep the trace unit powered and also * emulation of powerdown */ writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU, drvdata->base + TRCPDCR); writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU, drvdata->base + TRCPDCR); } /* Enable the trace unit */ writel_relaxed(1, drvdata->base + TRCPRGCTLR); Loading Loading @@ -313,10 +316,12 @@ static void etm4_disable_hw(void *info) CS_UNLOCK(drvdata->base); if (!drvdata->tupwr_disable) { /* power can be removed from the trace unit now */ control = readl_relaxed(drvdata->base + TRCPDCR); control &= ~TRCPDCR_PU; writel_relaxed(control, drvdata->base + TRCPDCR); } control = readl_relaxed(drvdata->base + TRCPRGCTLR); Loading Loading @@ -1041,6 +1046,9 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) etmdrvdata[drvdata->cpu] = drvdata; drvdata->tupwr_disable = of_property_read_bool(drvdata->dev->of_node, "qcom,tupwr-disable"); dev_info(dev, "CPU%d: %s initialized\n", drvdata->cpu, (char *)id->data); Loading drivers/hwtracing/coresight/coresight-etm4x.h +3 −1 Original line number Diff line number Diff line /* Copyright (c) 2014-2015, 2017, The Linux Foundation. All rights reserved. /* Copyright (c) 2014-2015, 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -345,6 +345,7 @@ struct etmv4_config { * @nooverflow: Indicate if overflow prevention is supported. * @atbtrig: If the implementation can support ATB triggers * @lpoverride: If the implementation can support low-power state over. * @tupwr_disable: If disable the support of keeping trace unit powered. * @config: structure holding configuration parameters. */ struct etmv4_drvdata { Loading Loading @@ -391,6 +392,7 @@ struct etmv4_drvdata { bool nooverflow; bool atbtrig; bool lpoverride; bool tupwr_disable; struct etmv4_config config; }; Loading Loading
Documentation/devicetree/bindings/arm/coresight.txt +3 −0 Original line number Diff line number Diff line Loading @@ -110,6 +110,9 @@ its hardware characteristcs. * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the source is considered to belong to CPU0. * qcom,tupwr-disable: For ETM, don't keep trace unit powered across power collapse. * Optional property for TMC: * arm,buffer-size: size of contiguous buffer space for TMC ETR Loading
arch/arm64/boot/dts/qcom/msm8937-coresight.dtsi +16 −0 Original line number Diff line number Diff line Loading @@ -462,6 +462,8 @@ reg = <0x619c000 0x1000>; cpu = <&CPU4>; qcom,tupwr-disable; coresight-name = "coresight-etm4"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -481,6 +483,8 @@ reg = <0x619d000 0x1000>; cpu = <&CPU5>; qcom,tupwr-disable; coresight-name = "coresight-etm5"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -500,6 +504,8 @@ reg = <0x619e000 0x1000>; cpu = <&CPU6>; qcom,tupwr-disable; coresight-name = "coresight-etm6"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -519,6 +525,8 @@ reg = <0x619f000 0x1000>; cpu = <&CPU7>; qcom,tupwr-disable; coresight-name = "coresight-etm7"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -538,6 +546,8 @@ reg = <0x61bc000 0x1000>; cpu = <&CPU0>; qcom,tupwr-disable; coresight-name = "coresight-etm0"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -557,6 +567,8 @@ reg = <0x61bd000 0x1000>; cpu = <&CPU1>; qcom,tupwr-disable; coresight-name = "coresight-etm1"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -576,6 +588,8 @@ reg = <0x61be000 0x1000>; cpu = <&CPU2>; qcom,tupwr-disable; coresight-name = "coresight-etm2"; clocks = <&clock_gcc clk_qdss_clk>, Loading @@ -594,6 +608,8 @@ arm,primecell-periphid = <0x000bb95d>; reg = <0x61bf000 0x1000>; qcom,tupwr-disable; coresight-name = "coresight-etm3"; cpu = <&CPU3>; Loading
arch/arm64/boot/dts/qcom/msm8953-coresight.dtsi +2 −0 Original line number Diff line number Diff line Loading @@ -505,6 +505,8 @@ reg = <0x619c000 0x1000>; cpu = <&CPU0>; qcom,tupwr-disable; coresight-name = "coresight-etm0"; clocks = <&clock_gcc clk_qdss_clk>, Loading
drivers/hwtracing/coresight/coresight-etm4x.c +18 −10 Original line number Diff line number Diff line Loading @@ -27,6 +27,7 @@ #include <linux/cpu.h> #include <linux/coresight.h> #include <linux/coresight-pmu.h> #include <linux/of.h> #include <linux/pm_wakeup.h> #include <linux/amba/bus.h> #include <linux/seq_file.h> Loading Loading @@ -167,12 +168,14 @@ static void etm4_enable_hw(void *info) writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0); writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1); if (!drvdata->tupwr_disable) { /* * Request to keep the trace unit powered and also * emulation of powerdown */ writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU, drvdata->base + TRCPDCR); writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU, drvdata->base + TRCPDCR); } /* Enable the trace unit */ writel_relaxed(1, drvdata->base + TRCPRGCTLR); Loading Loading @@ -313,10 +316,12 @@ static void etm4_disable_hw(void *info) CS_UNLOCK(drvdata->base); if (!drvdata->tupwr_disable) { /* power can be removed from the trace unit now */ control = readl_relaxed(drvdata->base + TRCPDCR); control &= ~TRCPDCR_PU; writel_relaxed(control, drvdata->base + TRCPDCR); } control = readl_relaxed(drvdata->base + TRCPRGCTLR); Loading Loading @@ -1041,6 +1046,9 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) etmdrvdata[drvdata->cpu] = drvdata; drvdata->tupwr_disable = of_property_read_bool(drvdata->dev->of_node, "qcom,tupwr-disable"); dev_info(dev, "CPU%d: %s initialized\n", drvdata->cpu, (char *)id->data); Loading
drivers/hwtracing/coresight/coresight-etm4x.h +3 −1 Original line number Diff line number Diff line /* Copyright (c) 2014-2015, 2017, The Linux Foundation. All rights reserved. /* Copyright (c) 2014-2015, 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -345,6 +345,7 @@ struct etmv4_config { * @nooverflow: Indicate if overflow prevention is supported. * @atbtrig: If the implementation can support ATB triggers * @lpoverride: If the implementation can support low-power state over. * @tupwr_disable: If disable the support of keeping trace unit powered. * @config: structure holding configuration parameters. */ struct etmv4_drvdata { Loading Loading @@ -391,6 +392,7 @@ struct etmv4_drvdata { bool nooverflow; bool atbtrig; bool lpoverride; bool tupwr_disable; struct etmv4_config config; }; Loading