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Commit 14cdd329 authored by Mao Jinlong's avatar Mao Jinlong
Browse files

ARM: dts: msm: Add tupwr-disable property for MSM8953 and MSM8937 



On MSM8953 and MSM8937, device will reset if cpu enters into power
collapse while etm trace unit is kept powered on. Add property to
control power of the trace unit for MSM8953 and MSM8937's ETM. Don't
keep trace unit powered across power collapse.

Change-Id: If1df95b2819b40a14749bada7b9a145ee77f788a
Signed-off-by: default avatarMao Jinlong <jinlmao@codeaurora.org>
parent 4c6d848d

arch/arm64/boot/dts/qcom/msm8937-coresight.dtsi

+16 −0
Original line number Diff line number Diff line
@@ -462,6 +462,8 @@ 


		reg = <0x619c000 0x1000>;

		cpu = <&CPU4>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm4";



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -481,6 +483,8 @@ 


		reg = <0x619d000 0x1000>;

		cpu = <&CPU5>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm5";



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -500,6 +504,8 @@ 


		reg = <0x619e000 0x1000>;

		cpu = <&CPU6>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm6";



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -519,6 +525,8 @@ 


		reg = <0x619f000 0x1000>;

		cpu = <&CPU7>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm7";



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -538,6 +546,8 @@ 


		reg = <0x61bc000 0x1000>;

		cpu = <&CPU0>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm0";



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -557,6 +567,8 @@ 


		reg = <0x61bd000 0x1000>;

		cpu = <&CPU1>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm1";



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -576,6 +588,8 @@ 


		reg = <0x61be000 0x1000>;

		cpu = <&CPU2>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm2";



		clocks = <&clock_gcc clk_qdss_clk>,
@@ -594,6 +608,8 @@ 
		arm,primecell-periphid = <0x000bb95d>;



		reg = <0x61bf000 0x1000>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm3";

		cpu = <&CPU3>;

arch/arm64/boot/dts/qcom/msm8953-coresight.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -505,6 +505,8 @@ 


		reg = <0x619c000 0x1000>;

		cpu = <&CPU0>;



		qcom,tupwr-disable;

		coresight-name = "coresight-etm0";



		clocks = <&clock_gcc clk_qdss_clk>,