Loading arch/arm/boot/dts/qcom/sdxpoorwills-cdp.dts +20 −0 Original line number Diff line number Diff line Loading @@ -34,6 +34,26 @@ status = "ok"; }; &sdhc_1 { vdd-supply = <&vreg_sd_mmc>; vdd-io-supply = <&pmxpoorwills_l7>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 10000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_cd_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_cd_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,devfreq,freq-table = <50000000 200000000>; cd-gpios = <&tlmm 93 0x1>; status = "ok"; }; &pmxpoorwills_vadc { chan@83 { label = "vph_pwr"; Loading arch/arm/boot/dts/qcom/sdxpoorwills-mtp.dts +20 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,26 @@ status = "ok"; }; &sdhc_1 { vdd-supply = <&vreg_sd_mmc>; vdd-io-supply = <&pmxpoorwills_l7>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 10000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_cd_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_cd_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,devfreq,freq-table = <50000000 200000000>; cd-gpios = <&tlmm 93 0x1>; status = "ok"; }; &pmxpoorwills_vadc { chan@83 { label = "vph_pwr"; Loading arch/arm/boot/dts/qcom/sdxpoorwills-pinctrl.dtsi +76 −0 Original line number Diff line number Diff line Loading @@ -1299,6 +1299,82 @@ }; }; /* SDC pin type */ sdc1_clk_on: sdc1_clk_on { config { pins = "sdc1_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc1_clk_off: sdc1_clk_off { config { pins = "sdc1_clk"; bias-disable; /* NO pull */ drive-strength = <2>; /* 2 MA */ }; }; sdc1_cmd_on: sdc1_cmd_on { config { pins = "sdc1_cmd"; bias-pull-up; /* pull up */ drive-strength = <10>; /* 10 MA */ }; }; sdc1_cmd_off: sdc1_cmd_off { config { pins = "sdc1_cmd"; num-grp-pins = <1>; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; sdc1_data_on: sdc1_data_on { config { pins = "sdc1_data"; bias-pull-up; /* pull up */ drive-strength = <10>; /* 10 MA */ }; }; sdc1_data_off: sdc1_data_off { config { pins = "sdc1_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; sdc1_cd_on: cd_on { mux { pins = "gpio93"; function = "gpio"; }; config { pins = "gpio93"; drive-strength = <2>; bias-pull-up; }; }; sdc1_cd_off: cd_off { mux { pins = "gpio93"; function = "gpio"; }; config { pins = "gpio93"; drive-strength = <2>; bias-disable; }; }; smb_int_default: smb_int_default { mux { pins = "gpio42"; Loading arch/arm/boot/dts/qcom/sdxpoorwills-regulator.dtsi +9 −0 Original line number Diff line number Diff line Loading @@ -11,6 +11,7 @@ */ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/gpio/gpio.h> &soc { /* RPMh regulators */ Loading Loading @@ -372,4 +373,12 @@ regulator-max-microvolt = <1800000>; regulator-always-on; }; vreg_sd_mmc: vreg_sd_mmc { compatible = "regulator-fixed"; regulator-name = "vreg_sd_mmc"; startup-delay-us = <4000>; enable-active-high; gpio = <&tlmm 92 GPIO_ACTIVE_HIGH>; }; }; arch/arm/boot/dts/qcom/sdxpoorwills.dtsi +40 −0 Original line number Diff line number Diff line Loading @@ -76,6 +76,7 @@ aliases { qpic_nand1 = &qnand_1; sdhc1 = &sdhc_1; /* SDC1 eMMC/SD/SDIO slot */ }; soc: soc { }; Loading Loading @@ -288,6 +289,45 @@ status = "disabled"; }; sdhc_1: sdhci@8804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x8804000 0x1000>; reg-names = "hc_mem"; interrupts = <0 210 0>, <0 227 0>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <4>; qcom,msm-bus,name = "sdhc1"; qcom,msm-bus,num-cases = <8>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ <78 512 1600 3200>, /* 400 KB/s*/ <78 512 80000 160000>, /* 20 MB/s */ <78 512 100000 200000>, /* 25 MB/s */ <78 512 200000 400000>, /* 50 MB/s */ <78 512 400000 800000>, /* 100 MB/s */ <78 512 400000 800000>, /* 200 MB/s */ <78 512 2048000 4096000>; /* Max. bandwidth */ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; /* PM QoS */ qcom,pm-qos-cpu-groups = <0x0>; qcom,pm-qos-cmdq-latency-us = <70>; qcom,pm-qos-legacy-latency-us = <70>; qcom,pm-qos-irq-type = "affine_cores"; qcom,pm-qos-irq-cpu = <0>; qcom,pm-qos-irq-latency = <70>; clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>; clock-names = "iface_clk", "core_clk"; status = "disabled"; }; qcom,msm-imem@1468B000 { compatible = "qcom,msm-imem"; reg = <0x1468B000 0x1000>; /* Address and size of IMEM */ Loading Loading
arch/arm/boot/dts/qcom/sdxpoorwills-cdp.dts +20 −0 Original line number Diff line number Diff line Loading @@ -34,6 +34,26 @@ status = "ok"; }; &sdhc_1 { vdd-supply = <&vreg_sd_mmc>; vdd-io-supply = <&pmxpoorwills_l7>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 10000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_cd_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_cd_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,devfreq,freq-table = <50000000 200000000>; cd-gpios = <&tlmm 93 0x1>; status = "ok"; }; &pmxpoorwills_vadc { chan@83 { label = "vph_pwr"; Loading
arch/arm/boot/dts/qcom/sdxpoorwills-mtp.dts +20 −0 Original line number Diff line number Diff line Loading @@ -33,6 +33,26 @@ status = "ok"; }; &sdhc_1 { vdd-supply = <&vreg_sd_mmc>; vdd-io-supply = <&pmxpoorwills_l7>; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <200 10000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_cd_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_cd_off>; qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 200000000>; qcom,devfreq,freq-table = <50000000 200000000>; cd-gpios = <&tlmm 93 0x1>; status = "ok"; }; &pmxpoorwills_vadc { chan@83 { label = "vph_pwr"; Loading
arch/arm/boot/dts/qcom/sdxpoorwills-pinctrl.dtsi +76 −0 Original line number Diff line number Diff line Loading @@ -1299,6 +1299,82 @@ }; }; /* SDC pin type */ sdc1_clk_on: sdc1_clk_on { config { pins = "sdc1_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc1_clk_off: sdc1_clk_off { config { pins = "sdc1_clk"; bias-disable; /* NO pull */ drive-strength = <2>; /* 2 MA */ }; }; sdc1_cmd_on: sdc1_cmd_on { config { pins = "sdc1_cmd"; bias-pull-up; /* pull up */ drive-strength = <10>; /* 10 MA */ }; }; sdc1_cmd_off: sdc1_cmd_off { config { pins = "sdc1_cmd"; num-grp-pins = <1>; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; sdc1_data_on: sdc1_data_on { config { pins = "sdc1_data"; bias-pull-up; /* pull up */ drive-strength = <10>; /* 10 MA */ }; }; sdc1_data_off: sdc1_data_off { config { pins = "sdc1_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; sdc1_cd_on: cd_on { mux { pins = "gpio93"; function = "gpio"; }; config { pins = "gpio93"; drive-strength = <2>; bias-pull-up; }; }; sdc1_cd_off: cd_off { mux { pins = "gpio93"; function = "gpio"; }; config { pins = "gpio93"; drive-strength = <2>; bias-disable; }; }; smb_int_default: smb_int_default { mux { pins = "gpio42"; Loading
arch/arm/boot/dts/qcom/sdxpoorwills-regulator.dtsi +9 −0 Original line number Diff line number Diff line Loading @@ -11,6 +11,7 @@ */ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/gpio/gpio.h> &soc { /* RPMh regulators */ Loading Loading @@ -372,4 +373,12 @@ regulator-max-microvolt = <1800000>; regulator-always-on; }; vreg_sd_mmc: vreg_sd_mmc { compatible = "regulator-fixed"; regulator-name = "vreg_sd_mmc"; startup-delay-us = <4000>; enable-active-high; gpio = <&tlmm 92 GPIO_ACTIVE_HIGH>; }; };
arch/arm/boot/dts/qcom/sdxpoorwills.dtsi +40 −0 Original line number Diff line number Diff line Loading @@ -76,6 +76,7 @@ aliases { qpic_nand1 = &qnand_1; sdhc1 = &sdhc_1; /* SDC1 eMMC/SD/SDIO slot */ }; soc: soc { }; Loading Loading @@ -288,6 +289,45 @@ status = "disabled"; }; sdhc_1: sdhci@8804000 { compatible = "qcom,sdhci-msm-v5"; reg = <0x8804000 0x1000>; reg-names = "hc_mem"; interrupts = <0 210 0>, <0 227 0>; interrupt-names = "hc_irq", "pwr_irq"; qcom,bus-width = <4>; qcom,msm-bus,name = "sdhc1"; qcom,msm-bus,num-cases = <8>; qcom,msm-bus,num-paths = <1>; qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */ <78 512 1600 3200>, /* 400 KB/s*/ <78 512 80000 160000>, /* 20 MB/s */ <78 512 100000 200000>, /* 25 MB/s */ <78 512 200000 400000>, /* 50 MB/s */ <78 512 400000 800000>, /* 100 MB/s */ <78 512 400000 800000>, /* 200 MB/s */ <78 512 2048000 4096000>; /* Max. bandwidth */ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 100000000 200000000 4294967295>; /* PM QoS */ qcom,pm-qos-cpu-groups = <0x0>; qcom,pm-qos-cmdq-latency-us = <70>; qcom,pm-qos-legacy-latency-us = <70>; qcom,pm-qos-irq-type = "affine_cores"; qcom,pm-qos-irq-cpu = <0>; qcom,pm-qos-irq-latency = <70>; clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, <&clock_gcc GCC_SDCC1_APPS_CLK>; clock-names = "iface_clk", "core_clk"; status = "disabled"; }; qcom,msm-imem@1468B000 { compatible = "qcom,msm-imem"; reg = <0x1468B000 0x1000>; /* Address and size of IMEM */ Loading