Loading arch/arm/boot/dts/qcom/sdxpoorwills.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -175,7 +175,7 @@ reg = <0x831000 0x200>; interrupts = <0 26 0>; status = "disabled"; clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, clocks = <&clock_gcc GCC_BLSP1_UART3_APPS_CLK>, <&clock_gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; }; Loading Loading
arch/arm/boot/dts/qcom/sdxpoorwills.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -175,7 +175,7 @@ reg = <0x831000 0x200>; interrupts = <0 26 0>; status = "disabled"; clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, clocks = <&clock_gcc GCC_BLSP1_UART3_APPS_CLK>, <&clock_gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; }; Loading