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Commit df79778c authored by Vicky Wallace's avatar Vicky Wallace
Browse files

ARM: dts: msm: Fix UART clock reference for sdxpoorwills 



UART registers starts the numbering from 0
so UART2 is the third instance which is BLSP1 UART3 clock.

CRs-Fixed: 2135284
Change-Id: Id94930ae8c1d4e68e1883eb54b3c7cb944d5ac09
Signed-off-by: default avatarVicky Wallace <vwallace@codeaurora.org>
parent 8e96f4f7

arch/arm/boot/dts/qcom/sdxpoorwills.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -175,7 +175,7 @@ 
		reg = <0x831000 0x200>;

		interrupts = <0 26 0>;

		status = "disabled";

		clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,

		clocks = <&clock_gcc GCC_BLSP1_UART3_APPS_CLK>,

			<&clock_gcc GCC_BLSP1_AHB_CLK>;

		clock-names = "core", "iface";

	};