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Commit da3e606d authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
Browse files

perf/x86: Dump DEBUGCTL in PMU dump 



LBRs and LBR freezing are controlled through the DEBUGCTL MSR. So
dump the state of DEBUGCTL too when dumping the PMU state.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1425059312-18217-3-git-send-email-andi@firstfloor.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 8882edf7

arch/x86/kernel/cpu/perf_event.c

+5 −1
Original line number Diff line number Diff line
@@ -1171,7 +1171,7 @@ static void x86_pmu_start(struct perf_event *event, int flags) 
void perf_event_print_debug(void)

{

	u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;

	u64 pebs;

	u64 pebs, debugctl;

	struct cpu_hw_events *cpuc;

	unsigned long flags;

	int cpu, idx;
@@ -1197,6 +1197,10 @@ void perf_event_print_debug(void) 
		pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);

		pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);

		pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);

		if (x86_pmu.lbr_nr) {

			rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);

			pr_info("CPU#%d: debugctl:   %016llx\n", cpu, debugctl);

		}

	}

	pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);