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Commit da0fa546 authored by Kyle Piefer's avatar Kyle Piefer Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Change the fence to ALLOW to prepare for SLUMBER 



After telling the GMU to prepare for SLUMBER, put the
fence in ALLOW mode. This prevents a situation where
the fence is in BLOCK or DROP mode but the GMU is not
available to change the mode back to ALLOW. This should
also be done when taking snapshots or handling RBBM
IRQs.

Also change gx_is_on() to not check the FENCE register.
When taking a snapshot, all that matters is that the
GX domain is powered on. If the fence is not in ALLOW
mode, we can just set it to ALLOW manually to read
the desired registers.

CRs-Fixed: 2085877
Change-Id: If72cbc8f1602dc718521f4c8bed6a02b782866bf
Signed-off-by: default avatarKyle Piefer <kpiefer@codeaurora.org>
parent 4edfb6b4

drivers/gpu/msm/adreno.c

+12 −1
Original line number Diff line number Diff line
@@ -599,7 +599,7 @@ static irqreturn_t adreno_irq_handler(struct kgsl_device *device) 
	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

	struct adreno_irq *irq_params = gpudev->irq;

	irqreturn_t ret = IRQ_NONE;

	unsigned int status = 0, tmp, int_bit;

	unsigned int status = 0, fence = 0, tmp, int_bit;

	int i;



	atomic_inc(&adreno_dev->pending_irq_refcnt);
@@ -614,6 +614,17 @@ static irqreturn_t adreno_irq_handler(struct kgsl_device *device) 
	if (gpudev->gpu_keepalive)

		gpudev->gpu_keepalive(adreno_dev, true);



	/*

	 * If the AHB fence is not in ALLOW mode when we receive an RBBM

	 * interrupt, something went wrong. Set a fault and change the

	 * fence to ALLOW so we can clear the interrupt.

	 */

	adreno_readreg(adreno_dev, ADRENO_REG_GMU_AO_AHB_FENCE_CTRL, &fence);

	if (fence != 0) {

		KGSL_DRV_CRIT_RATELIMIT(device, "AHB fence is stuck in ISR\n");

		return ret;

	}



	adreno_readreg(adreno_dev, ADRENO_REG_RBBM_INT_0_STATUS, &status);



	/*

drivers/gpu/msm/adreno.h

+1 −0
Original line number Diff line number Diff line
@@ -638,6 +638,7 @@ enum adreno_regs { 
	ADRENO_REG_VBIF_VERSION,

	ADRENO_REG_GBIF_HALT,

	ADRENO_REG_GBIF_HALT_ACK,

	ADRENO_REG_GMU_AO_AHB_FENCE_CTRL,

	ADRENO_REG_GMU_AO_INTERRUPT_EN,

	ADRENO_REG_GMU_AO_HOST_INTERRUPT_CLR,

	ADRENO_REG_GMU_AO_HOST_INTERRUPT_STATUS,

drivers/gpu/msm/adreno_a6xx.c

+7 −11
Original line number Diff line number Diff line
@@ -1290,21 +1290,12 @@ static bool a6xx_gx_is_on(struct adreno_device *adreno_dev) 
{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	unsigned int val;

	bool state;



	if (!kgsl_gmu_isenabled(device))

		return true;



	kgsl_gmu_regread(device, A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, &val);

	state = !(val & (GX_GDSC_POWER_OFF | GX_CLK_OFF));



	/* If GMU is holding on to the fence then we cannot dump any GX stuff */

	kgsl_gmu_regread(device, A6XX_GMU_AO_AHB_FENCE_CTRL, &val);

	if (val)

		return false;



	return state;



	return !(val & (GX_GDSC_POWER_OFF | GX_CLK_OFF));

}



/*
@@ -1380,7 +1371,7 @@ static int a6xx_notify_slumber(struct kgsl_device *device) 


	if (!ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) {

		ret = hfi_notify_slumber(gmu, perf_idx, bus_level);

		return ret;

		goto out;

	}



	kgsl_gmu_regwrite(device, A6XX_GMU_BOOT_SLUMBER_OPTION,
@@ -1406,6 +1397,9 @@ static int a6xx_notify_slumber(struct kgsl_device *device) 
		}

	}



out:

	/* Make sure the fence is in ALLOW mode */

	kgsl_gmu_regwrite(device, A6XX_GMU_AO_AHB_FENCE_CTRL, 0);

	return ret;

}
@@ -2948,6 +2942,8 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
				A6XX_GMU_ALWAYS_ON_COUNTER_L),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI,

				A6XX_GMU_ALWAYS_ON_COUNTER_H),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_AHB_FENCE_CTRL,

				A6XX_GMU_AO_AHB_FENCE_CTRL),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_INTERRUPT_EN,

				A6XX_GMU_AO_INTERRUPT_EN),

	ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_HOST_INTERRUPT_CLR,

drivers/gpu/msm/adreno_a6xx_snapshot.c

+6 −0
Original line number Diff line number Diff line
@@ -1577,6 +1577,12 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, 
	bool sptprac_on;

	unsigned int i;



	/* Make sure the fence is in ALLOW mode so registers can be read */

	kgsl_regwrite(device, A6XX_GMU_AO_AHB_FENCE_CTRL, 0);



	/* GMU TCM data dumped through AHB */

	a6xx_snapshot_gmu(adreno_dev, snapshot);



	sptprac_on = gpudev->sptprac_is_on(adreno_dev);



	/* Return if the GX is off */