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Commit 4edfb6b4 authored by Kyle Piefer's avatar Kyle Piefer Committed by Gerrit - the friendly Code Review server
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msm: kgsl: Make the WPTR retry delay shorter than hysteresis 



If the WPTR retry delay is longer than the IFPC main
hysteresis, the GMU could power up and collapse GX again
while we are waiting to retry. Shorten the delay, lengthen
the main hysteresis, and make a note of this for the future.

CRs-Fixed: 2085877
Change-Id: If852cb26e3728e03b3b3384f933a18d45abb0153
Signed-off-by: default avatarKyle Piefer <kpiefer@codeaurora.org>
parent 950f5925

drivers/gpu/msm/adreno_a6xx.c

+11 −2
Original line number Diff line number Diff line
@@ -1025,6 +1025,15 @@ static int timed_poll_check(struct kgsl_device *device, 
	return -EINVAL;

}



/*

 * The lowest 16 bits of this value are the number of XO clock cycles

 * for main hysteresis. This is the first hysteresis. Here we set it

 * to 0x5DC cycles, or 78.1 us. The highest 16 bits of this value are

 * the number of XO clock cycles for short hysteresis. This happens

 * after main hysteresis. Here we set it to 0xA cycles, or 0.5 us.

 */

#define GMU_PWR_COL_HYST 0x000A05DC



/*

 * a6xx_gmu_power_config() - Configure and enable GMU's low power mode

 * setting based on ADRENO feature flags.
@@ -1056,13 +1065,13 @@ static void a6xx_gmu_power_config(struct kgsl_device *device) 
		/* fall through */

	case GPU_HW_IFPC:

		kgsl_gmu_regwrite(device, A6XX_GMU_PWR_COL_INTER_FRAME_HYST,

				0x000A0080);

				GMU_PWR_COL_HYST);

		kgsl_gmu_regrmw(device, A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,

				IFPC_ENABLE_MASK);

		/* fall through */

	case GPU_HW_SPTP_PC:

		kgsl_gmu_regwrite(device, A6XX_GMU_PWR_COL_SPTPRAC_HYST,

				0x000A0080);

				GMU_PWR_COL_HYST);

		kgsl_gmu_regrmw(device, A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,

				SPTP_ENABLE_MASK);

		/* fall through */

drivers/gpu/msm/adreno_ringbuffer.c

+4 −2
Original line number Diff line number Diff line
@@ -83,10 +83,12 @@ static void adreno_get_submit_time(struct adreno_device *adreno_dev, 
/*

 * Wait time before trying to write the register again.

 * Hopefully the GMU has finished waking up during this delay.

 * This delay must be less than the IFPC main hysteresis or

 * the GMU will start shutting down before we try again.

 */

#define GMU_WAKEUP_DELAY 50

#define GMU_WAKEUP_DELAY 20

/* Max amount of tries to wake up the GMU. */

#define GMU_WAKEUP_RETRY_MAX 20

#define GMU_WAKEUP_RETRY_MAX 60



/*

 * Check the WRITEDROPPED0 bit in the