clk: mdss: write lane mode when powering on HDMI PHY

To improve the timing margin, lane mode selection
needs to be written during the HDMI PHY startup
sequence. This prevents a timing failure when
VDDCX or VCCA_CORE are applied rather than the
nominal value.

Change-Id: I2ed54f63903a473eca12fb4d8f3b542585397dae
Signed-off-by: Casey Piper <cpiper@codeaurora.org>