Merge "ARM: msm: dts: add vbif memory type settings for sdm845" (d7578aaa) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/display/msm/sde.txt

+4 −0

Original line number	Diff line number	Diff line
		@@ -234,6 +234,8 @@ Optional properties:
		of (pps, OT limit), where pps is pixel per second and
		OT limit is the write limit to apply if the given
		pps is not exceeded.
		- qcom,sde-vbif-memtype-0: Array of u32 vbif memory type settings, group 0
		- qcom,sde-vbif-memtype-1: Array of u32 vbif memory type settings, group 1
		- qcom,sde-wb-id: Array of writeback ids corresponding to the
		offsets defined in property: qcom,sde-wb-off.
		- qcom,sde-wb-clk-ctrl: Array of 2 cell property describing clk control
		@@ -527,6 +529,8 @@ Example:
		<124416000 4>, <248832000 16>;
		qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>,
		<124416000 4>, <248832000 16>;
		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;

		qcom,sde-dram-channels = <2>;
		qcom,sde-num-nrt-paths = <1>;

arch/arm64/boot/dts/qcom/sdm845-sde.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -136,6 +136,8 @@
		qcom,sde-vbif-off = <0>;
		qcom,sde-vbif-size = <0x1040>;
		qcom,sde-vbif-id = <0>;
		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;

		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
		qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+27 −0

Original line number	Diff line number	Diff line
		@@ -290,6 +290,8 @@ enum {
		VBIF_DYNAMIC_OT_WR_LIMIT,
		VBIF_QOS_RT_REMAP,
		VBIF_QOS_NRT_REMAP,
		VBIF_MEMTYPE_0,
		VBIF_MEMTYPE_1,
		VBIF_PROP_MAX,
		};

		@@ -530,6 +532,8 @@ static struct sde_prop_type vbif_prop[] = {
		PROP_TYPE_U32_ARRAY},
		{VBIF_QOS_NRT_REMAP, "qcom,sde-vbif-qos-nrt-remap", false,
		PROP_TYPE_U32_ARRAY},
		{VBIF_MEMTYPE_0, "qcom,sde-vbif-memtype-0", false, PROP_TYPE_U32_ARRAY},
		{VBIF_MEMTYPE_1, "qcom,sde-vbif-memtype-1", false, PROP_TYPE_U32_ARRAY},
		};

		static struct sde_prop_type reg_dma_prop[REG_DMA_PROP_MAX] = {
		@@ -1977,6 +1981,16 @@ static int sde_vbif_parse_dt(struct device_node *np,
		if (rc)
		goto end;

		rc = _validate_dt_entry(np, &vbif_prop[VBIF_MEMTYPE_0], 1,
		&prop_count[VBIF_MEMTYPE_0], NULL);
		if (rc)
		goto end;

		rc = _validate_dt_entry(np, &vbif_prop[VBIF_MEMTYPE_1], 1,
		&prop_count[VBIF_MEMTYPE_1], NULL);
		if (rc)
		goto end;

		sde_cfg->vbif_count = off_count;

		rc = _read_dt_entry(np, vbif_prop, ARRAY_SIZE(vbif_prop), prop_count,
		@@ -2125,6 +2139,19 @@ static int sde_vbif_parse_dt(struct device_node *np,
		if (vbif->qos_rt_tbl.npriority_lvl \|\|
		vbif->qos_nrt_tbl.npriority_lvl)
		set_bit(SDE_VBIF_QOS_REMAP, &vbif->features);

		vbif->memtype_count = prop_count[VBIF_MEMTYPE_0] +
		prop_count[VBIF_MEMTYPE_1];
		if (vbif->memtype_count > MAX_XIN_COUNT) {
		vbif->memtype_count = 0;
		SDE_ERROR("too many memtype defs, ignoring entries\n");
		}
		for (j = 0, k = 0; j < prop_count[VBIF_MEMTYPE_0]; j++)
		vbif->memtype[k++] = PROP_VALUE_ACCESS(
		prop_value, VBIF_MEMTYPE_0, j);
		for (j = 0; j < prop_count[VBIF_MEMTYPE_1]; j++)
		vbif->memtype[k++] = PROP_VALUE_ACCESS(
		prop_value, VBIF_MEMTYPE_1, j);
		}

		end:

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -60,6 +60,8 @@
		#define SDE_COLOR_PROCESS_MAJOR(version) (((version) & 0xFFFF0000) >> 16)
		#define SDE_COLOR_PROCESS_MINOR(version) ((version) & 0xFFFF)

		#define MAX_XIN_COUNT 16

		/**
		* Supported UBWC feature versions
		*/
		@@ -705,6 +707,8 @@ struct sde_vbif_qos_tbl {
		* @dynamic_ot_wr_tbl dynamic OT write configuration table
		* @qos_rt_tbl real-time QoS priority table
		* @qos_nrt_tbl non-real-time QoS priority table
		* @memtype_count number of defined memtypes
		* @memtype array of xin memtype definitions
		*/
		struct sde_vbif_cfg {
		SDE_HW_BLK_INFO;
		@@ -715,6 +719,8 @@ struct sde_vbif_cfg {
		struct sde_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
		struct sde_vbif_qos_tbl qos_rt_tbl;
		struct sde_vbif_qos_tbl qos_nrt_tbl;
		u32 memtype_count;
		u32 memtype[MAX_XIN_COUNT];
		};
		/**
		* struct sde_reg_dma_cfg - information of lut dma blocks

drivers/gpu/drm/msm/sde/sde_hw_vbif.c

+33 −0

Original line number	Diff line number	Diff line
		@@ -31,11 +31,43 @@
		#define VBIF_IN_WR_LIM_CONF2 0x00C8
		#define VBIF_OUT_RD_LIM_CONF0 0x00D0
		#define VBIF_OUT_WR_LIM_CONF0 0x00D4
		#define VBIF_OUT_AXI_AMEMTYPE_CONF0 0x0160
		#define VBIF_OUT_AXI_AMEMTYPE_CONF1 0x0164
		#define VBIF_XIN_HALT_CTRL0 0x0200
		#define VBIF_XIN_HALT_CTRL1 0x0204
		#define VBIF_XINL_QOS_RP_REMAP_000 0x0550
		#define VBIF_XINL_QOS_LVL_REMAP_000 0x0590

		static void sde_hw_set_mem_type(struct sde_hw_vbif *vbif,
		u32 xin_id, u32 value)
		{
		struct sde_hw_blk_reg_map *c;
		u32 reg_off;
		u32 bit_off;
		u32 reg_val;

		/*
		* Assume 4 bits per bit field, 8 fields per 32-bit register so
		* 16 bit fields maximum across two registers
		*/
		if (!vbif \|\| xin_id >= MAX_XIN_COUNT \|\| xin_id >= 16)
		return;

		c = &vbif->hw;

		if (xin_id >= 8) {
		xin_id -= 8;
		reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF1;
		} else {
		reg_off = VBIF_OUT_AXI_AMEMTYPE_CONF0;
		}
		bit_off = (xin_id & 0x7) * 4;
		reg_val = SDE_REG_READ(c, reg_off);
		reg_val &= ~(0x7 << bit_off);
		reg_val \|= (value & 0x7) << bit_off;
		SDE_REG_WRITE(c, reg_off, reg_val);
		}

		static void sde_hw_set_limit_conf(struct sde_hw_vbif *vbif,
		u32 xin_id, bool rd, u32 limit)
		{
		@@ -144,6 +176,7 @@ static void _setup_vbif_ops(struct sde_hw_vbif_ops *ops,
		ops->get_halt_ctrl = sde_hw_get_halt_ctrl;
		if (test_bit(SDE_VBIF_QOS_REMAP, &cap))
		ops->set_qos_remap = sde_hw_set_qos_remap;
		ops->set_mem_type = sde_hw_set_mem_type;
		}

		static const struct sde_vbif_cfg *_top_offset(enum sde_vbif vbif,