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Commit bcbbb5bd authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: add cdp support to sspp and wb modules"

parents b4f75f34 143f50cb

Documentation/devicetree/bindings/display/msm/sde.txt

+5 −3
Original line number Diff line number Diff line
@@ -132,8 +132,6 @@ Optional properties: 
				power collapse feature available or not.

- qcom,sde-has-mixer-gc:	Boolean property to indicate if mixer has gamma correction

				feature available or not.

- qcom,sde-has-cdp:		Boolean property to indicate if cdp feature is

				available or not.

- qcom,sde-sspp-clk-ctrl:	Array of offsets describing clk control

				offsets for dynamic clock gating. 1st value

				in the array represents offset of the control
@@ -319,6 +317,9 @@ Optional properties: 
				<fill level, lut hi, lut lo> in ascending fill level

				indicating the qos luts for cwb on sspp.

				Zero fill level on the last entry identifies the default lut.

- qcom,sde-cdp-setting:		Array of 2 cell property, with a format of

				<read enable, write enable> for cdp use cases in

				order of <real_time>, and <non_real_time>.



Bus Scaling Subnodes:

- qcom,sde-reg-bus:		Property to provide Bus scaling for register access for
@@ -447,7 +448,6 @@ Example: 
    qcom,sde-ubwc-static = <0x100>;

    qcom,sde-ubwc-swizzle = <0>;

    qcom,sde-panic-per-pipe;

    qcom,sde-has-cdp;

    qcom,sde-has-src-split;

    qcom,sde-has-dim-layer;

    qcom,sde-sspp-src-size = <0x100>;
@@ -517,6 +517,8 @@ Example: 
    qcom,sde-qos-lut-cwb =

            <0 0x75300000 0x00000000>;



    qcom,sde-cdp-setting = <1 1>, <1 0>;



    qcom,sde-vbif-off = <0 0>;

    qcom,sde-vbif-id = <0 1>;

    qcom,sde-vbif-default-ot-rd-limit = <32>;

drivers/gpu/drm/msm/sde/sde_encoder_phys.h

+2 −0
Original line number Diff line number Diff line
@@ -294,6 +294,7 @@ struct sde_encoder_phys_cmd { 
 * @bypass_irqreg:	Bypass irq register/unregister if non-zero

 * @wbdone_complete:	for wbdone irq synchronization

 * @wb_cfg:		Writeback hardware configuration

 * @cdp_cfg:		Writeback CDP configuration

 * @intf_cfg:		Interface hardware configuration

 * @wb_roi:		Writeback region-of-interest

 * @wb_fmt:		Writeback pixel format
@@ -315,6 +316,7 @@ struct sde_encoder_phys_wb { 
	u32 bypass_irqreg;

	struct completion wbdone_complete;

	struct sde_hw_wb_cfg wb_cfg;

	struct sde_hw_wb_cdp_cfg cdp_cfg;

	struct sde_hw_intf_cfg intf_cfg;

	struct sde_rect wb_roi;

	const struct sde_format *wb_fmt;

drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c

+18 −1
Original line number Diff line number Diff line
@@ -248,16 +248,18 @@ static void sde_encoder_phys_wb_setup_fb(struct sde_encoder_phys *phys_enc, 
	struct sde_encoder_phys_wb *wb_enc = to_sde_encoder_phys_wb(phys_enc);

	struct sde_hw_wb *hw_wb;

	struct sde_hw_wb_cfg *wb_cfg;

	struct sde_hw_wb_cdp_cfg *cdp_cfg;

	const struct msm_format *format;

	int ret, mmu_id;



	if (!phys_enc) {

	if (!phys_enc || !phys_enc->sde_kms || !phys_enc->sde_kms->catalog) {

		SDE_ERROR("invalid encoder\n");

		return;

	}



	hw_wb = wb_enc->hw_wb;

	wb_cfg = &wb_enc->wb_cfg;

	cdp_cfg = &wb_enc->cdp_cfg;

	memset(wb_cfg, 0, sizeof(struct sde_hw_wb_cfg));



	wb_cfg->intf_mode = phys_enc->intf_mode;
@@ -325,6 +327,21 @@ static void sde_encoder_phys_wb_setup_fb(struct sde_encoder_phys *phys_enc, 
	if (hw_wb->ops.setup_outformat)

		hw_wb->ops.setup_outformat(hw_wb, wb_cfg);



	if (hw_wb->ops.setup_cdp) {

		memset(cdp_cfg, 0, sizeof(struct sde_hw_wb_cdp_cfg));



		cdp_cfg->enable = phys_enc->sde_kms->catalog->perf.cdp_cfg

				[SDE_PERF_CDP_USAGE_NRT].wr_enable;

		cdp_cfg->ubwc_meta_enable =

				SDE_FORMAT_IS_UBWC(wb_cfg->dest.format);

		cdp_cfg->tile_amortize_enable =

				SDE_FORMAT_IS_UBWC(wb_cfg->dest.format) ||

				SDE_FORMAT_IS_TILE(wb_cfg->dest.format);

		cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;



		hw_wb->ops.setup_cdp(hw_wb, cdp_cfg);

	}



	if (hw_wb->ops.setup_outaddress)

		hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);

}

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+39 −6
Original line number Diff line number Diff line
@@ -136,7 +136,6 @@ enum sde_prop { 
	QSEED_TYPE,

	CSC_TYPE,

	PANIC_PER_PIPE,

	CDP,

	SRC_SPLIT,

	DIM_LAYER,

	SMART_DMA_REV,
@@ -165,6 +164,7 @@ enum { 
	PERF_QOS_LUT_MACROTILE,

	PERF_QOS_LUT_NRT,

	PERF_QOS_LUT_CWB,

	PERF_CDP_SETTING,

	PERF_PROP_MAX,

};
@@ -349,7 +349,6 @@ static struct sde_prop_type sde_prop[] = { 
	{QSEED_TYPE, "qcom,sde-qseed-type", false, PROP_TYPE_STRING},

	{CSC_TYPE, "qcom,sde-csc-type", false, PROP_TYPE_STRING},

	{PANIC_PER_PIPE, "qcom,sde-panic-per-pipe", false, PROP_TYPE_BOOL},

	{CDP, "qcom,sde-has-cdp", false, PROP_TYPE_BOOL},

	{SRC_SPLIT, "qcom,sde-has-src-split", false, PROP_TYPE_BOOL},

	{DIM_LAYER, "qcom,sde-has-dim-layer", false, PROP_TYPE_BOOL},

	{SMART_DMA_REV, "qcom,sde-smart-dma-rev", false, PROP_TYPE_STRING},
@@ -391,6 +390,8 @@ static struct sde_prop_type sde_perf_prop[] = { 
			PROP_TYPE_U32_ARRAY},

	{PERF_QOS_LUT_CWB, "qcom,sde-qos-lut-cwb", false,

			PROP_TYPE_U32_ARRAY},

	{PERF_CDP_SETTING, "qcom,sde-cdp-setting", false,

			PROP_TYPE_U32_ARRAY},

};



static struct sde_prop_type sspp_prop[] = {
@@ -1061,6 +1062,9 @@ static int sde_sspp_parse_dt(struct device_node *np, 


		set_bit(SDE_SSPP_SRC, &sspp->features);



		if (sde_cfg->has_cdp)

			set_bit(SDE_SSPP_CDP, &sspp->features);



		if (sde_cfg->ts_prefill_rev == 1) {

			set_bit(SDE_SSPP_TS_PREFILL, &sspp->features);

		} else if (sde_cfg->ts_prefill_rev == 2) {
@@ -1500,6 +1504,9 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg) 
		set_bit(SDE_WB_TRAFFIC_SHAPER, &wb->features);

		set_bit(SDE_WB_YUV_CONFIG, &wb->features);



		if (sde_cfg->has_cdp)

			set_bit(SDE_WB_CDP, &wb->features);



		set_bit(SDE_WB_QOS, &wb->features);

		if (sde_cfg->vbif_qos_nlvl == 8)

			set_bit(SDE_WB_QOS_8LVL, &wb->features);
@@ -2420,6 +2427,11 @@ static int sde_perf_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
	if (rc)

		goto freeprop;



	rc = _validate_dt_entry(np, &sde_perf_prop[PERF_CDP_SETTING], 1,

			&prop_count[PERF_CDP_SETTING], NULL);

	if (rc)

		goto freeprop;



	rc = _read_dt_entry(np, sde_perf_prop, ARRAY_SIZE(sde_perf_prop),

			prop_count, prop_exists, prop_value);

	if (rc)
@@ -2559,6 +2571,27 @@ static int sde_perf_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
		cfg->perf.qos_lut_tbl[j].nentry = count;

	}



	if (prop_exists[PERF_CDP_SETTING]) {

		const u32 prop_size = 2;

		u32 count = prop_count[PERF_CDP_SETTING] / prop_size;



		count = min_t(u32, count, SDE_PERF_CDP_USAGE_MAX);



		for (j = 0; j < count; j++) {

			cfg->perf.cdp_cfg[j].rd_enable =

					PROP_VALUE_ACCESS(prop_value,

					PERF_CDP_SETTING, j * prop_size);

			cfg->perf.cdp_cfg[j].wr_enable =

					PROP_VALUE_ACCESS(prop_value,

					PERF_CDP_SETTING, j * prop_size + 1);

			SDE_DEBUG("cdp usage:%d rd:%d wr:%d\n",

				j, cfg->perf.cdp_cfg[j].rd_enable,

				cfg->perf.cdp_cfg[j].wr_enable);

		}



		cfg->has_cdp = true;

	}



freeprop:

	kfree(prop_value);

end:
@@ -2760,6 +2793,10 @@ struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev) 
	if (rc)

		goto end;



	rc = sde_perf_parse_dt(np, sde_cfg);

	if (rc)

		goto end;



	rc = sde_rot_parse_dt(np, sde_cfg);

	if (rc)

		goto end;
@@ -2810,10 +2847,6 @@ struct sde_mdss_cfg *sde_hw_catalog_init(struct drm_device *dev, u32 hw_rev) 
	if (rc)

		goto end;



	rc = sde_perf_parse_dt(np, sde_cfg);

	if (rc)

		goto end;



	return sde_cfg;



end:

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+28 −3
Original line number Diff line number Diff line
@@ -79,7 +79,6 @@ enum { 
 * @SDE_MDP_UBWC_1_0,      This chipsets supports Universal Bandwidth

 *                         compression initial revision

 * @SDE_MDP_UBWC_1_5,      Universal Bandwidth compression version 1.5

 * @SDE_MDP_CDP,           Client driven prefetch

 * @SDE_MDP_MAX            Maximum value



 */
@@ -89,7 +88,6 @@ enum { 
	SDE_MDP_BWC,

	SDE_MDP_UBWC_1_0,

	SDE_MDP_UBWC_1_5,

	SDE_MDP_CDP,

	SDE_MDP_MAX

};
@@ -114,6 +112,7 @@ enum { 
 * @SDE_SSPP_SBUF,           SSPP support inline stream buffer

 * @SDE_SSPP_TS_PREFILL      Supports prefill with traffic shaper

 * @SDE_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec

 * @SDE_SSPP_CDP             Supports client driven prefetch

 * @SDE_SSPP_MAX             maximum value

 */

enum {
@@ -136,6 +135,7 @@ enum { 
	SDE_SSPP_SBUF,

	SDE_SSPP_TS_PREFILL,

	SDE_SSPP_TS_PREFILL_REC1,

	SDE_SSPP_CDP,

	SDE_SSPP_MAX

};
@@ -245,6 +245,7 @@ enum { 
 *                          the destination image

 * @SDE_WB_QOS,             Writeback supports QoS control, danger/safe/creq

 * @SDE_WB_QOS_8LVL,        Writeback supports 8-level QoS control

 * @SDE_WB_CDP              Writeback supports client driven prefetch

 * @SDE_WB_MAX              maximum value

 */

enum {
@@ -262,6 +263,7 @@ enum { 
	SDE_WB_XY_ROI_OFFSET,

	SDE_WB_QOS,

	SDE_WB_QOS_8LVL,

	SDE_WB_CDP,

	SDE_WB_MAX

};
@@ -728,6 +730,27 @@ struct sde_reg_dma_cfg { 
	u32 trigger_sel_off;

};



/**

 * Define CDP use cases

 * @SDE_PERF_CDP_UDAGE_RT: real-time use cases

 * @SDE_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD

 */

enum {

	SDE_PERF_CDP_USAGE_RT,

	SDE_PERF_CDP_USAGE_NRT,

	SDE_PERF_CDP_USAGE_MAX

};



/**

 * struct sde_perf_cdp_cfg - define CDP use case configuration

 * @rd_enable: true if read pipe CDP is enabled

 * @wr_enable: true if write pipe CDP is enabled

 */

struct sde_perf_cdp_cfg {

	bool rd_enable;

	bool wr_enable;

};



/**

 * struct sde_perf_cfg - performance control settings

 * @max_bw_low         low threshold of maximum bandwidth (kbps)
@@ -748,6 +771,7 @@ struct sde_reg_dma_cfg { 
 * @safe_lut_tbl: LUT tables for safe signals

 * @danger_lut_tbl: LUT tables for danger signals

 * @qos_lut_tbl: LUT tables for QoS signals

 * @cdp_cfg            cdp use case configurations

 */

struct sde_perf_cfg {

	u32 max_bw_low;
@@ -768,6 +792,7 @@ struct sde_perf_cfg { 
	u32 safe_lut_tbl[SDE_QOS_LUT_USAGE_MAX];

	u32 danger_lut_tbl[SDE_QOS_LUT_USAGE_MAX];

	struct sde_qos_lut_tbl qos_lut_tbl[SDE_QOS_LUT_USAGE_MAX];

	struct sde_perf_cdp_cfg cdp_cfg[SDE_PERF_CDP_USAGE_MAX];

};



/**
@@ -785,7 +810,7 @@ struct sde_perf_cfg { 
 * @csc_type           csc or csc_10bit support.

 * @smart_dma_rev      Supported version of SmartDMA feature.

 * @has_src_split      source split feature status

 * @has_cdp            Client driver prefetch feature status

 * @has_cdp            Client driven prefetch feature status

 * @has_wb_ubwc        UBWC feature supported on WB

 * @ubwc_version       UBWC feature version (0x0 for not supported)

 * @has_sbuf           indicate if stream buffer is available