Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit d5b7f387 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: clk-cpu-osm: Remove writes to ITM registers 



The Gold and Silver control ITM registers will be written to
and configured by an entity outside of HLOS. Remove the
accesses in the HLOS clock driver.

Change-Id: Ie5f442bb9bf34718ecca8424d255965f951c76fc
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent bfcf69c1

Documentation/devicetree/bindings/arm/msm/qcom,osm.txt

+4 −6
Original line number Diff line number Diff line
@@ -25,9 +25,8 @@ Properties: 
	Value type: <stringlist>

	Definition: Address names. Must be "osm_l3_base", "osm_pwrcl_base",

		    "osm_perfcl_base", "l3_pll", "pwrcl_pll", "perfcl_pll",

		    "l3_sequencer", "pwrcl_sequencer", "perfcl_sequencer" or

		    "apps_itm_ctl". Optionally, "l3_efuse", "pwrcl_efuse"

		    "perfcl_efuse".

		    "l3_sequencer", "pwrcl_sequencer", "perfcl_sequencer".

		    Optionally, "l3_efuse", "pwrcl_efuse", "perfcl_efuse".

		    Must be specified in the same order as the corresponding

		    addresses are specified in the reg property.
@@ -350,12 +349,11 @@ Example: 
			<0x178b0000 0x1000>,

			<0x17d42400 0x0c00>,

			<0x17d44400 0x0c00>,

			<0x17d46c00 0x0c00>,

			<0x17810090 0x8>;

			<0x17d46c00 0x0c00>;

		reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base",

			"l3_pll", "pwrcl_pll", "perfcl_pll",

			"l3_sequencer", "pwrcl_sequencer",

			"perfcl_sequencer", "apps_itm_ctl";

			"perfcl_sequencer";



		vdd-l3-supply = <&apc0_l3_vreg>;

		vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;

arch/arm64/boot/dts/qcom/sdm845.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -868,12 +868,11 @@ 
			<0x178b0000 0x1000>,

			<0x17d42400 0x0c00>,

			<0x17d44400 0x0c00>,

			<0x17d46c00 0x0c00>,

			<0x17810090 0x8>;

			<0x17d46c00 0x0c00>;

		reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base",

			"l3_pll", "pwrcl_pll", "perfcl_pll",

			"l3_sequencer", "pwrcl_sequencer",

			"perfcl_sequencer", "apps_itm_ctl";

			"perfcl_sequencer";



		vdd-l3-supply = <&apc0_l3_vreg>;

		vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;

drivers/clk/qcom/clk-cpu-osm.c

+0 −26
Original line number Diff line number Diff line
@@ -2266,8 +2266,6 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) 
	struct clk_osm *c;

	struct device *dev = &pdev->dev;

	struct clk_onecell_data *clk_data;

	struct resource *res;

	void *vbase;

	char l3speedbinstr[] = "qcom,l3-speedbin0-v0";

	char perfclspeedbinstr[] = "qcom,perfcl-speedbin0-v0";

	char pwrclspeedbinstr[] = "qcom,pwrcl-speedbin0-v0";
@@ -2475,30 +2473,6 @@ static int clk_cpu_osm_driver_probe(struct platform_device *pdev) 
				(0x39 | (perfcl_clk.apm_threshold_vc << 6)));

	}



	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

							"apps_itm_ctl");

	if (!res) {

		dev_err(&pdev->dev,

			"Unable to get platform resource for apps_itm_ctl\n");

		return -ENOMEM;

	}



	vbase = devm_ioremap(&pdev->dev, res->start,

						resource_size(res));

	if (!vbase) {

		dev_err(&pdev->dev,

				"Unable to map in apps_itm_ctl base\n");

		return -ENOMEM;

	}



	val = readl_relaxed(vbase + 0x0);

	val &= ~BIT(0);

	writel_relaxed(val, vbase + 0x0);



	val = readl_relaxed(vbase + 0x4);

	val &= ~BIT(0);

	writel_relaxed(val, vbase + 0x4);



	/*

	 * Perform typical secure-world HW initialization

	 * as necessary.