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Commit d2e6d30a authored by Markos Chandras's avatar Markos Chandras
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MIPS: mm: page: Add MIPS R6 support



The MIPS R6 pref instruction only has 9 bits for the immediate
field so skip the micro-assembler PREF instruction if the offset
does not fit in 9 bits. Moreover, bit 30 (Pref_PrepareForStore) is
no longer valid in MIPS R6, so we change the default for all MIPS R6
processors to bit 5 (Pref_StoreStreamed).

Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent 8c56208a
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