Merge "power: smb5: Handle QC2.0 charger collapse gracefully" (d1ce22cb) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/power/supply/qcom/smb5-lib.c

+72 −0

Original line number	Diff line number	Diff line
		@@ -2875,7 +2875,9 @@ irqreturn_t usbin_uv_irq_handler(int irq, void *data)
		struct smb_irq_data *irq_data = data;
		struct smb_charger *chg = irq_data->parent_data;
		struct storm_watch *wdata;
		const struct apsd_result *apsd = smblib_get_apsd_result(chg);
		int rc;
		u8 stat = 0, max_pulses = 0;

		smblib_dbg(chg, PR_INTERRUPT, "IRQ: %s\n", irq_data->name);

		@@ -2946,6 +2948,54 @@ irqreturn_t usbin_uv_irq_handler(int irq, void *data)

		wdata = &chg->irq_info[SWITCHER_POWER_OK_IRQ].irq_data->storm_data;
		reset_storm_count(wdata);

		if (!chg->non_compliant_chg_detected &&
		apsd->pst == POWER_SUPPLY_TYPE_USB_HVDCP) {
		rc = smblib_read(chg, QC_CHANGE_STATUS_REG, &stat);
		if (rc < 0)
		smblib_err(chg,
		"Couldn't read CHANGE_STATUS_REG rc=%d\n", rc);

		if (stat & QC_5V_BIT)
		return IRQ_HANDLED;

		rc = smblib_read(chg, HVDCP_PULSE_COUNT_MAX_REG, &max_pulses);
		if (rc < 0)
		smblib_err(chg,
		"Couldn't read QC2 max pulses rc=%d\n", rc);

		chg->non_compliant_chg_detected = true;
		chg->qc2_max_pulses = (max_pulses &
		HVDCP_PULSE_COUNT_MAX_QC2_MASK);

		if (stat & QC_12V_BIT) {
		rc = smblib_masked_write(chg, HVDCP_PULSE_COUNT_MAX_REG,
		HVDCP_PULSE_COUNT_MAX_QC2_MASK,
		HVDCP_PULSE_COUNT_MAX_QC2_9V);
		if (rc < 0)
		smblib_err(chg, "Couldn't force max pulses to 9V rc=%d\n",
		rc);

		} else if (stat & QC_9V_BIT) {
		rc = smblib_masked_write(chg, HVDCP_PULSE_COUNT_MAX_REG,
		HVDCP_PULSE_COUNT_MAX_QC2_MASK,
		HVDCP_PULSE_COUNT_MAX_QC2_5V);
		if (rc < 0)
		smblib_err(chg, "Couldn't force max pulses to 5V rc=%d\n",
		rc);

		}

		rc = smblib_masked_write(chg, USBIN_AICL_OPTIONS_CFG_REG,
		SUSPEND_ON_COLLAPSE_USBIN_BIT,
		0);
		if (rc < 0)
		smblib_err(chg, "Couldn't turn off SUSPEND_ON_COLLAPSE_USBIN_BIT rc=%d\n",
		rc);

		smblib_rerun_apsd(chg);
		}

		return IRQ_HANDLED;
		}

		@@ -3578,6 +3628,28 @@ static void typec_src_removal(struct smb_charger *chg)
		smblib_err(chg, "Couldn't set USBIN_ADAPTER_ALLOW_5V_OR_9V_TO_12V rc=%d\n",
		rc);

		/*
		* if non-compliant charger caused UV, restore original max pulses
		* and turn SUSPEND_ON_COLLAPSE_USBIN_BIT back on.
		*/
		if (chg->non_compliant_chg_detected) {
		rc = smblib_masked_write(chg, HVDCP_PULSE_COUNT_MAX_REG,
		HVDCP_PULSE_COUNT_MAX_QC2_MASK,
		chg->qc2_max_pulses);
		if (rc < 0)
		smblib_err(chg, "Couldn't restore max pulses rc=%d\n",
		rc);

		rc = smblib_masked_write(chg, USBIN_AICL_OPTIONS_CFG_REG,
		SUSPEND_ON_COLLAPSE_USBIN_BIT,
		SUSPEND_ON_COLLAPSE_USBIN_BIT);
		if (rc < 0)
		smblib_err(chg, "Couldn't turn on SUSPEND_ON_COLLAPSE_USBIN_BIT rc=%d\n",
		rc);

		chg->non_compliant_chg_detected = false;
		}

		if (chg->use_extcon)
		smblib_notify_device_mode(chg, false);

drivers/power/supply/qcom/smb5-lib.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -419,6 +419,8 @@ struct smb_charger {
		u32 wa_flags;
		int boost_current_ua;
		bool dbc_usbov;
		int qc2_max_pulses;
		bool non_compliant_chg_detected;

		/* extcon for VBUS / ID notification to USB for uUSB */
		struct extcon_dev *extcon;

drivers/power/supply/qcom/smb5-reg.h

+14 −0

Original line number	Diff line number	Diff line
		@@ -223,6 +223,18 @@ enum {
		#define SINGLE_DECREMENT_BIT BIT(1)
		#define SINGLE_INCREMENT_BIT BIT(0)

		#define USB_CMD_PULLDOWN_REG (USBIN_BASE + 0x45)
		#define EN_PULLDOWN_USB_IN_BIT BIT(0)

		#define HVDCP_PULSE_COUNT_MAX_REG (USBIN_BASE + 0x5B)
		#define HVDCP_PULSE_COUNT_MAX_QC2_MASK GENMASK(7, 6)
		enum {
		HVDCP_PULSE_COUNT_MAX_QC2_5V,
		HVDCP_PULSE_COUNT_MAX_QC2_9V,
		HVDCP_PULSE_COUNT_MAX_QC2_12V,
		HVDCP_PULSE_COUNT_MAX_QC2_INVALID
		};

		#define USBIN_ADAPTER_ALLOW_CFG_REG (USBIN_BASE + 0x60)
		enum {
		USBIN_ADAPTER_ALLOW_5V = 0,
		@@ -259,6 +271,8 @@ enum {
		#define USBIN_CURRENT_LIMIT_CFG_REG (USBIN_BASE + 0x70)

		#define USBIN_AICL_OPTIONS_CFG_REG (USBIN_BASE + 0x80)
		#define SUSPEND_ON_COLLAPSE_USBIN_BIT BIT(7)
		#define USBIN_AICL_PERIODIC_RERUN_EN_BIT BIT(4)
		#define USBIN_AICL_ADC_EN_BIT BIT(3)

		#define USBIN_5V_AICL_THRESHOLD_REG (USBIN_BASE + 0x81)