Merge tag 'samsung-cleanup' of... (d073d7a1) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/arm/Samsung-S3C24XX/DMA.txt

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		S3C2410 DMA
		===========

		Introduction
		------------

		The kernel provides an interface to manage DMA transfers
		using the DMA channels in the CPU, so that the central
		duty of managing channel mappings, and programming the
		channel generators is in one place.


		DMA Channel Ordering
		--------------------

		Many of the range do not have connections for the DMA
		channels to all sources, which means that some devices
		have a restricted number of channels that can be used.

		To allow flexibility for each CPU type and board, the
		DMA code can be given a DMA ordering structure which
		allows the order of channel search to be specified, as
		well as allowing the prohibition of certain claims.

		struct s3c24xx_dma_order has a list of channels, and
		each channel within has a slot for a list of DMA
		channel numbers. The slots are searched in order for
		the presence of a DMA channel number with DMA_CH_VALID
		or-ed in.

		If the order has the flag DMA_CH_NEVER set, then after
		checking the channel list, the system will return no
		found channel, thus denying the request.

		A board support file can call s3c24xx_dma_order_set()
		to register a complete ordering set. The routine will
		copy the data, so the original can be discarded with
		__initdata.


		Authour
		-------

		Ben Dooks,
		Copyright (c) 2007 Ben Dooks, Simtec Electronics
		Licensed under the GPL v2

arch/arm/mach-exynos/exynos.c

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		@@ -27,20 +27,16 @@
		#include <asm/mach/map.h>
		#include <asm/memory.h>

		#include <mach/map.h>

		#include "common.h"
		#include "mfc.h"
		#include "regs-pmu.h"
		#include "regs-sys.h"

		void __iomem *pmu_base_addr;

		static struct map_desc exynos4_iodesc[] __initdata = {
		{
		.virtual = (unsigned long)S3C_VA_SYS,
		.pfn = __phys_to_pfn(EXYNOS4_PA_SYSCON),
		.length = SZ_64K,
		.type = MT_DEVICE,
		}, {
		.virtual = (unsigned long)S5P_VA_SROMC,
		.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
		.length = SZ_4K,
		@@ -70,11 +66,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {

		static struct map_desc exynos5_iodesc[] __initdata = {
		{
		.virtual = (unsigned long)S3C_VA_SYS,
		.pfn = __phys_to_pfn(EXYNOS5_PA_SYSCON),
		.length = SZ_64K,
		.type = MT_DEVICE,
		}, {
		.virtual = (unsigned long)S5P_VA_SROMC,
		.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
		.length = SZ_4K,
		@@ -213,32 +204,6 @@ static void __init exynos_init_irq(void)

		static void __init exynos_dt_machine_init(void)
		{
		struct device_node *i2c_np;
		const char *i2c_compat = "samsung,s3c2440-i2c";
		unsigned int tmp;
		int id;

		/*
		* Exynos5's legacy i2c controller and new high speed i2c
		* controller have muxed interrupt sources. By default the
		* interrupts for 4-channel HS-I2C controller are enabled.
		* If node for first four channels of legacy i2c controller
		* are available then re-configure the interrupts via the
		* system register.
		*/
		if (soc_is_exynos5()) {
		for_each_compatible_node(i2c_np, NULL, i2c_compat) {
		if (of_device_is_available(i2c_np)) {
		id = of_alias_get_id(i2c_np, "i2c");
		if (id < 4) {
		tmp = readl(EXYNOS5_SYS_I2C_CFG);
		writel(tmp & ~(0x1 << id),
		EXYNOS5_SYS_I2C_CFG);
		}
		}
		}
		}

		/*
		* This is called from smp_prepare_cpus if we've built for SMP, but
		* we still need to set it up for PM and firmware ops if not.

arch/arm/mach-exynos/include/mach/dma.h

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		/*
		* Copyright (C) 2010 Samsung Electronics Co. Ltd.
		* Jaswinder Singh <jassi.brar@samsung.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		* the Free Software Foundation; either version 2 of the License, or
		* (at your option) any later version.
		*
		* This program is distributed in the hope that it will be useful,
		* but WITHOUT ANY WARRANTY; without even the implied warranty of
		* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		* GNU General Public License for more details.
		*
		* You should have received a copy of the GNU General Public License
		* along with this program; if not, write to the Free Software
		* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
		*/

		#ifndef __MACH_DMA_H
		#define __MACH_DMA_H

		/* This platform uses the common DMA API driver for PL330 */
		#include <plat/dma-pl330.h>

		#endif /* __MACH_DMA_H */

arch/arm/mach-exynos/include/mach/map.h

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		@@ -24,9 +24,6 @@

		#define EXYNOS_PA_CHIPID 0x10000000

		#define EXYNOS4_PA_SYSCON 0x10010000
		#define EXYNOS5_PA_SYSCON 0x10050100

		#define EXYNOS4_PA_CMU 0x10030000
		#define EXYNOS5_PA_CMU 0x10010000

arch/arm/mach-exynos/pm.c

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		@@ -23,12 +23,13 @@
		#include <asm/smp_scu.h>
		#include <asm/suspend.h>

		#include <mach/map.h>

		#include <plat/pm-common.h>

		#include "common.h"
		#include "exynos-pmu.h"
		#include "regs-pmu.h"
		#include "regs-sys.h"

		static inline void __iomem *exynos_boot_vector_addr(void)
		{