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Commit d0181354 authored by Duc Dang's avatar Duc Dang
Browse files

arm64: dts: Add Designware I2C controller DTS entries for X-Gene v2 SoC platform 



This patch adds DTS entries for Designware I2C controllers used in
APM X-Gene v2 evaluation platform (Merlin board).

X-Gene v2 has total 5 I2C controllers. On Merlin board only I2C1
and I2C4 controllers are available in Linux, where the other 3
controllers are used for management purpose (power management,
BMC function).

Signed-off-by: default avatarDuc Dang <dhdang@apm.com>
parent 62ff9683

arch/arm64/boot/dts/apm/apm-shadowcat.dtsi

+59 −0
Original line number Diff line number Diff line
@@ -232,6 +232,18 @@ 
				clock-output-names = "ahbclk";

			};



			sbapbclk: sbapbclk@1704c000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&ahbclk 0>;

				reg = <0x0 0x1704c000 0x0 0x2000>;

				reg-names = "div-reg";

				divider-offset = <0x10>;

				divider-width = <0x2>;

				divider-shift = <0x0>;

				clock-output-names = "sbapbclk";

			};



			sdioclk: sdioclk@1f2ac000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;
@@ -301,6 +313,32 @@ 
				enable-mask = <0x10>;

				clock-output-names = "rngpkaclk";

			};



			i2c1clk: i2c1clk@17000000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&sbapbclk 0>;

				reg = <0x0 0x17000000 0x0 0x2000>;

				reg-names = "csr-reg";

				csr-offset = <0xc>;

				csr-mask = <0x4>;

				enable-offset = <0x10>;

				enable-mask = <0x4>;

				clock-output-names = "i2c1clk";

			};



			i2c4clk: i2c4clk@1704c000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&sbapbclk 0>;

				reg = <0x0 0x1704c000 0x0 0x1000>;

				reg-names = "csr-reg";

				csr-offset = <0x0>;

				csr-mask = <0x40>;

				enable-offset = <0x8>;

				enable-mask = <0x40>;

				clock-output-names = "i2c4clk";

			};

		};



		scu: system-clk-controller@17000000 {
@@ -589,5 +627,26 @@ 
			interrupts = <0x0 0x41 0x4>;

			clocks = <&rngpkaclk 0>;

		};



		i2c1: i2c1@10511000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,designware-i2c";

			reg = <0x0 0x10511000 0x0 0x1000>;

			interrupts = <0 0x45 0x4>;

			#clock-cells = <1>;

			clocks = <&i2c1clk 0>;

			bus_num = <1>;

		};



		i2c4: i2c4@10640000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "snps,designware-i2c";

			reg = <0x0 0x10640000 0x0 0x1000>;

			interrupts = <0 0x3A 0x4>;

			clocks = <&i2c4clk 0>;

			bus_num = <4>;

		};

	};

};