Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ceccd298 authored by Chew, Chiau Ee's avatar Chew, Chiau Ee Committed by Wolfram Sang
Browse files

i2c: designware-pci: add 10-bit addressing mode functionality for BYT I2C 



All the I2C controllers on Intel BayTrail LPSS subsystem able
to support 10-bit addressing mode functionality.

Signed-off-by: default avatarChew, Chiau Ee <chiau.ee.chew@intel.com>
Signed-off-by: default avatarOng, Boon Leong <boon.leong.ong@intel.com>
Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
parent 0977f273

drivers/i2c/busses/i2c-designware-pcidrv.c

+11 −6
Original line number Diff line number Diff line
@@ -64,12 +64,19 @@ struct dw_pci_controller { 
	u32 tx_fifo_depth;

	u32 rx_fifo_depth;

	u32 clk_khz;

	u32 functionality;

};



#define INTEL_MID_STD_CFG  (DW_IC_CON_MASTER |			\

				DW_IC_CON_SLAVE_DISABLE |	\

				DW_IC_CON_RESTART_EN)



#define DW_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C |			\

					I2C_FUNC_SMBUS_BYTE |		\

					I2C_FUNC_SMBUS_BYTE_DATA |	\

					I2C_FUNC_SMBUS_WORD_DATA |	\

					I2C_FUNC_SMBUS_I2C_BLOCK)



static struct  dw_pci_controller  dw_pci_controllers[] = {

	[moorestown_0] = {

		.bus_num     = 0,
@@ -140,6 +147,7 @@ static struct dw_pci_controller dw_pci_controllers[] = { 
		.tx_fifo_depth = 32,

		.rx_fifo_depth = 32,

		.clk_khz = 100000,

		.functionality = I2C_FUNC_10BIT_ADDR,

	},

};

static struct i2c_algorithm i2c_dw_algo = {
@@ -212,12 +220,9 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev, 
	dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;

	dev->base = pcim_iomap_table(pdev)[0];

	dev->dev = &pdev->dev;

	dev->functionality =

		I2C_FUNC_I2C |

		I2C_FUNC_SMBUS_BYTE |

		I2C_FUNC_SMBUS_BYTE_DATA |

		I2C_FUNC_SMBUS_WORD_DATA |

		I2C_FUNC_SMBUS_I2C_BLOCK;

	dev->functionality = controller->functionality |

				DW_DEFAULT_FUNCTIONALITY;



	dev->master_cfg =  controller->bus_cfg;



	pci_set_drvdata(pdev, dev);