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Commit cd763368 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru
Browse files

ARM: dts: msm: add the SDE Display Port PLL dtsi node for SDM845 



Add the device tree node to enable the SDE Display Port device for
SDM845. This includes the core clocks, register offsets, PMIC
regulators and other settings needed for the DP PLL.

Change-Id: I32cf4c83e521f178479b1ad307c9b42d43ea7a9c
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent 6f0508d3

arch/arm64/boot/dts/qcom/sdm845-sde-pll.dtsi

+42 −0
Original line number Diff line number Diff line
@@ -64,4 +64,46 @@ 
			};

		};

	};



	mdss_dp_pll: qcom,mdss_dp_pll@c011000 {

		compatible = "qcom,mdss_dp_pll_10nm";

		label = "MDSS DP PLL";

		cell-index = <0>;

		#clock-cells = <1>;



		reg = <0x088ea000 0x200>,

		      <0x088eaa00 0x200>,

		      <0x088ea200 0x200>,

		      <0x088ea600 0x200>,

		      <0xaf03000 0x8>;

		reg-names = "pll_base", "phy_base", "ln_tx0_base",

			"ln_tx1_base", "gdsc_base";



		gdsc-supply = <&mdss_core_gdsc>;



		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,

			 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

			 <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;

		clock-names = "iface_clk", "ref_clk_src", "ref_clk",

			"cfg_ahb_clk", "pipe_clk";

		clock-rate = <0>;



		qcom,platform-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,platform-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "gdsc";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};



		};

	};



};