clk: qcom: mdss: add upstream clock framework support for 10nm DP PLL

Model and configure the 10nm MDSS Display Port PLL for SDM845. Add
change to define the clocks and their relevant ops for DP VCO,
divider and mux using upstream clock framework.

Change-Id: If190a18cb6ec900c8bf5d93604d1d288aeee243d
Signed-off-by: Govinda Rajulu Chenna <gchenna@codeaurora.org>
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>