Loading drivers/gpu/drm/msm/sde/sde_hw_catalog.c +12 −4 Original line number Diff line number Diff line Loading @@ -1886,16 +1886,24 @@ static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) cfg->mdp[0].highest_bank_bit = DEFAULT_SDE_HIGHEST_BANK_BIT; rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type); if (!rc && !strcmp(type, "qseedv3")) if (!rc && !strcmp(type, "qseedv3")) { cfg->qseed_type = SDE_SSPP_SCALER_QSEED3; else if (!rc && !strcmp(type, "qseedv2")) } else if (!rc && !strcmp(type, "qseedv2")) { cfg->qseed_type = SDE_SSPP_SCALER_QSEED2; } else if (rc) { SDE_DEBUG("invalid QSEED configuration\n"); rc = 0; } rc = of_property_read_string(np, sde_prop[CSC_TYPE].prop_name, &type); if (!rc && !strcmp(type, "csc")) if (!rc && !strcmp(type, "csc")) { cfg->csc_type = SDE_SSPP_CSC; else if (!rc && !strcmp(type, "csc-10bit")) } else if (!rc && !strcmp(type, "csc-10bit")) { cfg->csc_type = SDE_SSPP_CSC_10BIT; } else if (rc) { SDE_DEBUG("invalid csc configuration\n"); rc = 0; } /* * Current SDE support only Smart DMA 2.0. Loading drivers/gpu/drm/msm/sde/sde_plane.c +2 −2 Original line number Diff line number Diff line Loading @@ -1825,11 +1825,11 @@ static void _sde_plane_install_properties(struct drm_plane *plane, 0, ~0, 0, PLANE_PROP_SCALER_V1); } if (psde->features & BIT(SDE_SSPP_CSC)) { if (psde->features & BIT(SDE_SSPP_CSC) || psde->features & BIT(SDE_SSPP_CSC_10BIT)) msm_property_install_volatile_range( &psde->property_info, "csc_v1", 0x0, 0, ~0, 0, PLANE_PROP_CSC_V1); } if (psde->features & BIT(SDE_SSPP_HSIC)) { snprintf(feature_name, sizeof(feature_name), "%s%d", Loading Loading
drivers/gpu/drm/msm/sde/sde_hw_catalog.c +12 −4 Original line number Diff line number Diff line Loading @@ -1886,16 +1886,24 @@ static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) cfg->mdp[0].highest_bank_bit = DEFAULT_SDE_HIGHEST_BANK_BIT; rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type); if (!rc && !strcmp(type, "qseedv3")) if (!rc && !strcmp(type, "qseedv3")) { cfg->qseed_type = SDE_SSPP_SCALER_QSEED3; else if (!rc && !strcmp(type, "qseedv2")) } else if (!rc && !strcmp(type, "qseedv2")) { cfg->qseed_type = SDE_SSPP_SCALER_QSEED2; } else if (rc) { SDE_DEBUG("invalid QSEED configuration\n"); rc = 0; } rc = of_property_read_string(np, sde_prop[CSC_TYPE].prop_name, &type); if (!rc && !strcmp(type, "csc")) if (!rc && !strcmp(type, "csc")) { cfg->csc_type = SDE_SSPP_CSC; else if (!rc && !strcmp(type, "csc-10bit")) } else if (!rc && !strcmp(type, "csc-10bit")) { cfg->csc_type = SDE_SSPP_CSC_10BIT; } else if (rc) { SDE_DEBUG("invalid csc configuration\n"); rc = 0; } /* * Current SDE support only Smart DMA 2.0. Loading
drivers/gpu/drm/msm/sde/sde_plane.c +2 −2 Original line number Diff line number Diff line Loading @@ -1825,11 +1825,11 @@ static void _sde_plane_install_properties(struct drm_plane *plane, 0, ~0, 0, PLANE_PROP_SCALER_V1); } if (psde->features & BIT(SDE_SSPP_CSC)) { if (psde->features & BIT(SDE_SSPP_CSC) || psde->features & BIT(SDE_SSPP_CSC_10BIT)) msm_property_install_volatile_range( &psde->property_info, "csc_v1", 0x0, 0, ~0, 0, PLANE_PROP_CSC_V1); } if (psde->features & BIT(SDE_SSPP_HSIC)) { snprintf(feature_name, sizeof(feature_name), "%s%d", Loading