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Commit cc4371fd authored by Kyle Piefer's avatar Kyle Piefer
Browse files

msm: kgsl: Update HW CGC settings 



For best performance, it is required that some of
the hardware CGC settings are changed to new values.
Update them in the register structure.

Change-Id: I97792c383ea542a13eda53f9ede9d0e948e1efba
Signed-off-by: default avatarKyle Piefer <kpiefer@codeaurora.org>
parent b16c6077

drivers/gpu/msm/adreno_a6xx.c

+13 −13
Original line number Diff line number Diff line
@@ -73,14 +73,14 @@ static const struct kgsl_hwcg_reg a630_hwcg_regs[] = { 
	{A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},

	{A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},

	{A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},

	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_DELAY_SP1, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_DELAY_SP2, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_DELAY_SP3, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_HYST_SP0, 0x00000080},

	{A6XX_RBBM_CLOCK_HYST_SP1, 0x00000080},

	{A6XX_RBBM_CLOCK_HYST_SP2, 0x00000080},

	{A6XX_RBBM_CLOCK_HYST_SP3, 0x00000080},

	{A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},

	{A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},

	{A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},

	{A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},

	{A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF},

	{A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},

	{A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},

	{A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
@@ -105,10 +105,10 @@ static const struct kgsl_hwcg_reg a630_hwcg_regs[] = { 
	{A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x07777777},

	{A6XX_RBBM_CLOCK_HYST3_TP1, 0x07777777},

	{A6XX_RBBM_CLOCK_HYST3_TP2, 0x07777777},

	{A6XX_RBBM_CLOCK_HYST3_TP3, 0x07777777},

	{A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},

	{A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},

	{A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},

	{A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
@@ -153,7 +153,7 @@ static const struct kgsl_hwcg_reg a630_hwcg_regs[] = { 
	{A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},

	{A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},

	{A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},

	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},

	{A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},

	{A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},

	{A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},

	{A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222},