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Commit b16c6077 authored by Kyle Piefer's avatar Kyle Piefer
Browse files

msm: kgsl: Change SP HW CGC settings 



For best performance, change the HW clock gating
settings for the SP blocks.

Change-Id: Icd1d819c8499561234dc602dbe4ec4dc7f315129
Signed-off-by: default avatarKyle Piefer <kpiefer@codeaurora.org>
parent 0c3e7520

drivers/gpu/msm/adreno_a6xx.c

+4 −4
Original line number Diff line number Diff line
@@ -65,10 +65,10 @@ struct kgsl_hwcg_reg { 
	unsigned int val;

};

static const struct kgsl_hwcg_reg a630_hwcg_regs[] = {

	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},

	{A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},

	{A6XX_RBBM_CLOCK_CNTL_SP1, 0x02222222},

	{A6XX_RBBM_CLOCK_CNTL_SP2, 0x02222222},

	{A6XX_RBBM_CLOCK_CNTL_SP3, 0x02222222},

	{A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},

	{A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},

	{A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},