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Commit ca7bb283 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "serial: msm_geni: Add bus voting support" into msm-4.9

parents ea09d373 3e694cc6

Documentation/devicetree/bindings/serial/qcom,msm-geni-uart.txt

+5 −0
Original line number Diff line number Diff line
@@ -16,6 +16,10 @@ Required properties: 
  Should be "active" and "sleep" for the pin confuguration when core is active

  or when entering sleep state.



Optional properties:

- qcom,bus-mas: contains the bus master id needed to put in bus bandwidth votes

		for inter-connect buses.



Example:

qupv3_uart11: qcom,qup_uart@0xa88000 {

	compatible = "qcom,msm-geni-uart";
@@ -29,4 +33,5 @@ qupv3_uart11: qcom,qup_uart@0xa88000 { 
	pinctrl-0 = <&qup_1_uart_3_active>;

	pinctrl-1 = <&qup_1_uart_3_sleep>;

	interrupts = <0 355 0>;

	qcom,bus-mas = <MASTER_BLSP_2>;

};

drivers/tty/serial/msm_geni_serial.c

+26 −0
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ 
#include <linux/serial_core.h>

#include <linux/tty.h>

#include <linux/tty_flip.h>

#include <linux/msm-bus.h>

#include <linux/msm-bus-board.h>



/* UART specific GENI registers */

#define SE_UART_LOOPBACK_CFG		(0x22C)
@@ -95,6 +97,10 @@ 
#define GENI_UART_NR_PORTS	(15)

#define DEF_FIFO_DEPTH_WORDS	(16)

#define DEF_FIFO_WIDTH_BITS	(32)

#define UART_CORE2X_VOTE	(10000)

#define DEFAULT_SE_CLK		(19200000)

#define DEFAULT_BUS_WIDTH	(4)





struct msm_geni_serial_port {

	struct uart_port uport;
@@ -1257,6 +1263,25 @@ static int msm_geni_serial_probe(struct platform_device *pdev) 
	}



	uport->dev = &pdev->dev;



	if (!(of_property_read_u32(pdev->dev.of_node, "qcom,bus-mas",

					&dev_port->serial_rsc.bus_mas))) {

		dev_port->serial_rsc.bus_bw =

				msm_bus_scale_register(

					dev_port->serial_rsc.bus_mas,

					MSM_BUS_SLAVE_EBI_CH0,

					(char *)dev_name(&pdev->dev),

					false);

		if (IS_ERR_OR_NULL(dev_port->serial_rsc.bus_bw)) {

			ret = PTR_ERR(dev_port->serial_rsc.bus_bw);

			goto exit_geni_serial_probe;

		}

		dev_port->serial_rsc.ab = UART_CORE2X_VOTE;

		dev_port->serial_rsc.ib = DEFAULT_SE_CLK * DEFAULT_BUS_WIDTH;

	} else {

		dev_info(&pdev->dev, "No bus master specified");

	}



	dev_port->serial_rsc.se_clk = devm_clk_get(&pdev->dev, "se-clk");

	if (IS_ERR(dev_port->serial_rsc.se_clk)) {

		ret = PTR_ERR(dev_port->serial_rsc.se_clk);
@@ -1364,6 +1389,7 @@ static int msm_geni_serial_remove(struct platform_device *pdev) 
			(struct uart_driver *)port->uport.private_data;



	uart_remove_one_port(drv, &port->uport);

	msm_bus_scale_unregister(port->serial_rsc.bus_bw);

	return 0;

}

include/linux/qcom-geni-se.h

+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ struct se_geni_rsc { 
	struct clk *m_ahb_clk;

	struct clk *s_ahb_clk;

	struct msm_bus_client_handle *bus_bw;

	unsigned int bus_mas;

	unsigned long ab;

	unsigned long ib;

	struct pinctrl *geni_pinctrl;