Merge "clk: qcom: gcc-sdm845: Keep the gcc_aggre_noc_pcie_tbu_clk enabled" (c98c3c6b) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/clk/qcom/gcc-sdm845.c

+16 −19

Original line number	Diff line number	Diff line
		@@ -1341,6 +1341,7 @@ static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_aggre_noc_pcie_tbu_clk",
		.flags = CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -1499,6 +1500,7 @@ static struct clk_branch gcc_camera_ahb_clk = {
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_camera_ahb_clk",
		.flags = CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -1525,6 +1527,7 @@ static struct clk_branch gcc_camera_xo_clk = {
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_camera_xo_clk",
		.flags = CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -1619,7 +1622,7 @@ static struct clk_branch gcc_cpuss_ahb_clk = {
		"gcc_cpuss_ahb_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.flags = CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -1633,6 +1636,7 @@ static struct clk_branch gcc_cpuss_dvm_bus_clk = {
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_cpuss_dvm_bus_clk",
		.flags = CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -1648,6 +1652,7 @@ static struct clk_branch gcc_cpuss_gnoc_clk = {
		.enable_mask = BIT(22),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_cpuss_gnoc_clk",
		.flags = CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -1694,6 +1699,7 @@ static struct clk_branch gcc_disp_ahb_clk = {
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_disp_ahb_clk",
		.flags = CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -1754,6 +1760,7 @@ static struct clk_branch gcc_disp_xo_clk = {
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_disp_xo_clk",
		.flags = CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -1823,6 +1830,7 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_gpu_cfg_ahb_clk",
		.flags = CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -2778,7 +2786,7 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
		"gcc_cpuss_ahb_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.flags = CLK_SET_RATE_PARENT \| CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -3551,6 +3559,7 @@ static struct clk_branch gcc_video_ahb_clk = {
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_video_ahb_clk",
		.flags = CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -3577,6 +3586,7 @@ static struct clk_branch gcc_video_xo_clk = {
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_video_xo_clk",
		.flags = CLK_IS_CRITICAL,
		.ops = &clk_branch2_ops,
		},
		},
		@@ -4012,6 +4022,10 @@ static void gcc_sdm845_fixup_sdm845v2(void)
		240000000;
		gcc_ufs_phy_axi_clk_src.freq_tbl =
		ftbl_gcc_ufs_card_axi_clk_src_sdm845_v2;
		gcc_aggre_noc_pcie_tbu_clk.clkr.hw.init = &(struct clk_init_data){
		.name = "gcc_aggre_noc_pcie_tbu_clk",
		.ops = &clk_branch2_ops,
		};
		}

		static int gcc_sdm845_fixup(struct platform_device *pdev)
		@@ -4084,23 +4098,6 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
		regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3);
		regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3);

		/* Keep these CPUSS clocks enabled always */
		clk_prepare_enable(gcc_cpuss_ahb_clk.clkr.hw.clk);
		clk_prepare_enable(gcc_sys_noc_cpuss_ahb_clk.clkr.hw.clk);
		clk_prepare_enable(gcc_cpuss_dvm_bus_clk.clkr.hw.clk);
		clk_prepare_enable(gcc_cpuss_gnoc_clk.clkr.hw.clk);

		/* Keep the core XO clock enabled always */
		clk_prepare_enable(gcc_camera_xo_clk.clkr.hw.clk);
		clk_prepare_enable(gcc_disp_xo_clk.clkr.hw.clk);
		clk_prepare_enable(gcc_video_xo_clk.clkr.hw.clk);

		/* Enable for core register access */
		clk_prepare_enable(gcc_gpu_cfg_ahb_clk.clkr.hw.clk);
		clk_prepare_enable(gcc_disp_ahb_clk.clkr.hw.clk);
		clk_prepare_enable(gcc_camera_ahb_clk.clkr.hw.clk);
		clk_prepare_enable(gcc_video_ahb_clk.clkr.hw.clk);

		/* DFS clock registration */
		ret = qcom_cc_register_rcg_dfs(pdev, &gcc_sdm845_dfs_desc);
		if (ret)