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Commit d8a82794 authored by Deepak Katragadda's avatar Deepak Katragadda
Browse files

clk: qcom: gcc-sdm845: Keep the gcc_aggre_noc_pcie_tbu_clk enabled 



The gcc_aggre_noc_pcie_tbu_clk should never be gated on SDM845 v1.
Take this opportunity to add the CLK_IS_CRITICAL flag to the other
peripheral clocks that are being kept enabled by making an explicit
clk_prepare_enable call.

Change-Id: I949ed9968c432309c9008d483eaa0a4b23c7fc3d
Signed-off-by: default avatarDeepak Katragadda <dkatraga@codeaurora.org>
parent 70be28c9

drivers/clk/qcom/gcc-sdm845.c

+16 −19
Original line number Diff line number Diff line
@@ -1291,6 +1291,7 @@ static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_aggre_noc_pcie_tbu_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1449,6 +1450,7 @@ static struct clk_branch gcc_camera_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_camera_ahb_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1475,6 +1477,7 @@ static struct clk_branch gcc_camera_xo_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_camera_xo_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1569,7 +1572,7 @@ static struct clk_branch gcc_cpuss_ahb_clk = { 
				"gcc_cpuss_ahb_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1583,6 +1586,7 @@ static struct clk_branch gcc_cpuss_dvm_bus_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_cpuss_dvm_bus_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1598,6 +1602,7 @@ static struct clk_branch gcc_cpuss_gnoc_clk = { 
		.enable_mask = BIT(22),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_cpuss_gnoc_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1644,6 +1649,7 @@ static struct clk_branch gcc_disp_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_disp_ahb_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1704,6 +1710,7 @@ static struct clk_branch gcc_disp_xo_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_disp_xo_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1773,6 +1780,7 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_gpu_cfg_ahb_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2728,7 +2736,7 @@ static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { 
				"gcc_cpuss_ahb_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3501,6 +3509,7 @@ static struct clk_branch gcc_video_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_video_ahb_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3527,6 +3536,7 @@ static struct clk_branch gcc_video_xo_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_video_xo_clk",

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3958,6 +3968,10 @@ static void gcc_sdm845_fixup_sdm845v2(void) 
		240000000;

	gcc_ufs_phy_axi_clk_src.freq_tbl =

		ftbl_gcc_ufs_card_axi_clk_src_sdm845_v2;

	gcc_aggre_noc_pcie_tbu_clk.clkr.hw.init = &(struct clk_init_data){

			.name = "gcc_aggre_noc_pcie_tbu_clk",

			.ops = &clk_branch2_ops,

		};

}



static int gcc_sdm845_fixup(struct platform_device *pdev)
@@ -4030,23 +4044,6 @@ static int gcc_sdm845_probe(struct platform_device *pdev) 
	regmap_update_bits(regmap, GCC_MMSS_MISC, 0x3, 0x3);

	regmap_update_bits(regmap, GCC_GPU_MISC, 0x3, 0x3);



	/* Keep these CPUSS clocks enabled always */

	clk_prepare_enable(gcc_cpuss_ahb_clk.clkr.hw.clk);

	clk_prepare_enable(gcc_sys_noc_cpuss_ahb_clk.clkr.hw.clk);

	clk_prepare_enable(gcc_cpuss_dvm_bus_clk.clkr.hw.clk);

	clk_prepare_enable(gcc_cpuss_gnoc_clk.clkr.hw.clk);



	/* Keep the core XO clock enabled always */

	clk_prepare_enable(gcc_camera_xo_clk.clkr.hw.clk);

	clk_prepare_enable(gcc_disp_xo_clk.clkr.hw.clk);

	clk_prepare_enable(gcc_video_xo_clk.clkr.hw.clk);



	/* Enable for core register access */

	clk_prepare_enable(gcc_gpu_cfg_ahb_clk.clkr.hw.clk);

	clk_prepare_enable(gcc_disp_ahb_clk.clkr.hw.clk);

	clk_prepare_enable(gcc_camera_ahb_clk.clkr.hw.clk);

	clk_prepare_enable(gcc_video_ahb_clk.clkr.hw.clk);



	/* DFS clock registration */

	ret = qcom_cc_register_rcg_dfs(pdev, &gcc_sdm845_dfs_desc);

	if (ret)