Merge remote-tracking branches 'asoc/fix/atmel', 'asoc/fix/intel',...

Audio Binding for Arndale boards

Required properties:

- compatible : Can be the following,

			"samsung,arndale-rt5631"

- samsung,audio-cpu: The phandle of the Samsung I2S controller

- samsung,audio-codec: The phandle of the audio codec

Optional:

- samsung,model: The name of the sound-card

Arndale Boards has many audio daughter cards, one of them is

rt5631/alc5631. Below example shows audio bindings for rt5631/

alc5631 based codec.

Example:

sound {

		compatible = "samsung,arndale-rt5631";

		samsung,audio-cpu = <&i2s0>

		samsung,audio-codec = <&rt5631>;

};

- rx-num-evt : FIFO levels.

- sram-size-playback : size of sram to be allocated during playback

- sram-size-capture  : size of sram to be allocated during capture

- interrupts : Interrupt numbers for McASP, currently not used by the driver

- interrupts : Interrupt numbers for McASP

- interrupt-names : Known interrupt names are "tx" and "rx"

- pinctrl-0: Should specify pin control group used for this controller.

- pinctrl-names: Should contain only one value - "default", for more details

Audio complex for Eukrea boards with tlv320aic23 codec.

Required properties:

  - compatible		: "eukrea,asoc-tlv320"

  - eukrea,model	: The user-visible name of this sound complex.

  - ssi-controller	: The phandle of the SSI controller.

  - fsl,mux-int-port	: The internal port of the i.MX audio muxer (AUDMUX).

  - fsl,mux-ext-port	: The external port of the i.MX audio muxer.

Note: The AUDMUX port numbering should start at 1, which is consistent with

  - clock-names		: Includes the following entries:

	"core"		  The core clock used to access registers

	"extal"		The esai baud clock for esai controller used to derive

			HCK, SCK and FS.

	"fsys"		The system clock derived from ahb clock used to derive

			HCK, SCK and FS.

	"extal"		  The esai baud clock for esai controller used to

			  derive HCK, SCK and FS.

	"fsys"		  The system clock derived from ahb clock used to

			  derive HCK, SCK and FS.

  - fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.

    This number is the maximum allowed value for TFCR[TFWM] or RFCR[RFWM].

  - fsl,fifo-depth	: The number of elements in the transmit and receive

			  FIFOs. This number is the maximum allowed value for

			  TFCR[TFWM] or RFCR[RFWM].

  - fsl,esai-synchronous: This is a boolean property. If present, indicating

    that ESAI would work in the synchronous mode, which means all the settings

    for Receiving would be duplicated from Transmition related registers.

			  that ESAI would work in the synchronous mode, which

			  means all the settings for Receiving would be

			  duplicated from Transmition related registers.

  - big-endian : If this property is absent, the native endian mode will

    be in use as default, or the big endian mode will be in use for all the

    device registers.

  - big-endian		: If this property is absent, the native endian mode

			  will be in use as default, or the big endian mode

			  will be in use for all the device registers.

Example:

  - clocks		: Contains an entry for each entry in clock-names.

  - clock-names		: Includes the following entries:

	"core"		The core clock of spdif controller

	"core"		  The core clock of spdif controller.

	"rxtx<0-7>"	  Clock source list for tx and rx clock.

			This clock list should be identical to

			the source list connecting to the spdif

			clock mux in "SPDIF Transceiver Clock

			Diagram" of SoC reference manual. It

			can also be referred to TxClk_Source

			bit of register SPDIF_STC.

   - big-endian : If this property is absent, the native endian mode will

   be in use as default, or the big endian mode will be in use for all the

   device registers.

			  This clock list should be identical to the source

			  list connecting to the spdif clock mux in "SPDIF

			  Transceiver Clock Diagram" of SoC reference manual.

			  It can also be referred to TxClk_Source bit of

			  register SPDIF_STC.

   - big-endian		: If this property is absent, the native endian mode

			  will be in use as default, or the big endian mode

			  will be in use for all the device registers.

Example: