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Commit bfcd6204 authored by Chanwoo Choi's avatar Chanwoo Choi Committed by MyungJoo Ham
Browse files

PM / devfreq: exynos: Remove unused exynos4/5 busfreq driver 



This patch removes the unused exynos4/5 busfreq driver. Instead,
generic exynos-bus frequency driver support the all Exynos SoCs.

Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: default avatarMyungJoo Ham <myungjoo.ham@samsung.com>
Acked-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
parent 38279cac

drivers/devfreq/Kconfig

+0 −22
Original line number Diff line number Diff line
@@ -90,28 +90,6 @@ config ARM_EXYNOS_BUS_DEVFREQ 
	  and adjusts the operating frequencies and voltages with OPP support.

	  This does not yet operate with optimal voltages.



config ARM_EXYNOS4_BUS_DEVFREQ

	bool "ARM Exynos4210/4212/4412 Memory Bus DEVFREQ Driver"

	depends on (CPU_EXYNOS4210 || SOC_EXYNOS4212 || SOC_EXYNOS4412) && !ARCH_MULTIPLATFORM

	select DEVFREQ_GOV_SIMPLE_ONDEMAND

	select PM_OPP

	help

	  This adds the DEVFREQ driver for Exynos4210 memory bus (vdd_int)

	  and Exynos4212/4412 memory interface and bus (vdd_mif + vdd_int).

	  It reads PPMU counters of memory controllers and adjusts

	  the operating frequencies and voltages with OPP support.

	  This does not yet operate with optimal voltages.



config ARM_EXYNOS5_BUS_DEVFREQ

	tristate "ARM Exynos5250 Bus DEVFREQ Driver"

	depends on SOC_EXYNOS5250

	select DEVFREQ_GOV_SIMPLE_ONDEMAND

	select PM_OPP

	help

	  This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int).

	  It reads PPMU counters of memory controllers and adjusts the

	  operating frequencies and voltages with OPP support.



config ARM_TEGRA_DEVFREQ

       tristate "Tegra DEVFREQ Driver"

       depends on ARCH_TEGRA_124_SOC

drivers/devfreq/Makefile

+0 −2
Original line number Diff line number Diff line
@@ -8,8 +8,6 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o 


# DEVFREQ Drivers

obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ)	+= exynos-bus.o

obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ)	+= exynos/

obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ)	+= exynos/

obj-$(CONFIG_ARM_TEGRA_DEVFREQ)		+= tegra-devfreq.o



# DEVFREQ Event Drivers

drivers/devfreq/exynos/Makefile

deleted100644 → 0
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Original line number Diff line number Diff line 
# Exynos DEVFREQ Drivers

obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ)	+= exynos_ppmu.o exynos4_bus.o

obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ)	+= exynos_ppmu.o exynos5_bus.o

drivers/devfreq/exynos/exynos4_bus.c

deleted100644 → 0
+0 −1055

File deleted.

Preview size limit exceeded, changes collapsed.

drivers/devfreq/exynos/exynos4_bus.h

deleted100644 → 0
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Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013 Samsung Electronics Co., Ltd.

 *		http://www.samsung.com/

 *

 * EXYNOS4 BUS header

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/



#ifndef __DEVFREQ_EXYNOS4_BUS_H

#define __DEVFREQ_EXYNOS4_BUS_H __FILE__



#include <mach/map.h>



#define EXYNOS4_CLKDIV_LEFTBUS			(S5P_VA_CMU + 0x04500)

#define EXYNOS4_CLKDIV_STAT_LEFTBUS		(S5P_VA_CMU + 0x04600)



#define EXYNOS4_CLKDIV_RIGHTBUS			(S5P_VA_CMU + 0x08500)

#define EXYNOS4_CLKDIV_STAT_RIGHTBUS		(S5P_VA_CMU + 0x08600)



#define EXYNOS4_CLKDIV_TOP			(S5P_VA_CMU + 0x0C510)

#define EXYNOS4_CLKDIV_CAM			(S5P_VA_CMU + 0x0C520)

#define EXYNOS4_CLKDIV_MFC			(S5P_VA_CMU + 0x0C528)



#define EXYNOS4_CLKDIV_STAT_TOP			(S5P_VA_CMU + 0x0C610)

#define EXYNOS4_CLKDIV_STAT_MFC			(S5P_VA_CMU + 0x0C628)



#define EXYNOS4210_CLKGATE_IP_IMAGE		(S5P_VA_CMU + 0x0C930)

#define EXYNOS4212_CLKGATE_IP_IMAGE		(S5P_VA_CMU + 0x04930)



#define EXYNOS4_CLKDIV_DMC0			(S5P_VA_CMU + 0x10500)

#define EXYNOS4_CLKDIV_DMC1			(S5P_VA_CMU + 0x10504)

#define EXYNOS4_CLKDIV_STAT_DMC0		(S5P_VA_CMU + 0x10600)

#define EXYNOS4_CLKDIV_STAT_DMC1		(S5P_VA_CMU + 0x10604)



#define EXYNOS4_DMC_PAUSE_CTRL			(S5P_VA_CMU + 0x11094)

#define EXYNOS4_DMC_PAUSE_ENABLE		(1 << 0)



#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT		(0)

#define EXYNOS4_CLKDIV_DMC0_ACP_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT)

#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT	(4)

#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK	(0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT)

#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT		(8)

#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT)

#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT		(12)

#define EXYNOS4_CLKDIV_DMC0_DMC_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT)

#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT		(16)

#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT)

#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT		(20)

#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)

#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT		(24)

#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT)

#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT	(28)

#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK		(0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)



#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT	(0)

#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK	(0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT)

#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT		(4)

#define EXYNOS4_CLKDIV_DMC1_C2C_MASK		(0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT)

#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT		(8)

#define EXYNOS4_CLKDIV_DMC1_PWI_MASK		(0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT)

#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT	(12)

#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK	(0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)

#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT		(16)

#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK		(0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT)

#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT		(24)

#define EXYNOS4_CLKDIV_DMC1_DPM_MASK		(0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT)



#define EXYNOS4_CLKDIV_MFC_SHIFT		(0)

#define EXYNOS4_CLKDIV_MFC_MASK			(0x7 << EXYNOS4_CLKDIV_MFC_SHIFT)



#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT	(0)

#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT)

#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT	(4)

#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK		(0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT)

#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT	(8)

#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT)

#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT	(12)

#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT)

#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT	(16)

#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK		(0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)

#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT	(20)

#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK	(0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT)

#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT	(24)

#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK	(0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT)



#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT		(0)

#define EXYNOS4_CLKDIV_BUS_GDLR_MASK		(0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT)

#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT		(4)

#define EXYNOS4_CLKDIV_BUS_GPLR_MASK		(0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)



#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT		(0)

#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK		(0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT)

#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT		(4)

#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK		(0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT)

#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT		(8)

#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK		(0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT)

#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT		(12)

#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK		(0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)



#define EXYNOS4_CLKDIV_CAM1			(S5P_VA_CMU + 0x0C568)



#define EXYNOS4_CLKDIV_STAT_CAM1		(S5P_VA_CMU + 0x0C668)



#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT		(0)

#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK		(0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)



#endif /* __DEVFREQ_EXYNOS4_BUS_H */