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Commit 38279cac authored by Chanwoo Choi's avatar Chanwoo Choi Committed by MyungJoo Ham
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PM / devfreq: exynos: Add the detailed correlation between sub-blocks and power line



This patch adds the detailed correlation between sub-blocks and power line
for Exynos3250, Exynos4210 and Exynos4x12.

Signed-off-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Acked-by: default avatarMyungJoo Ham <myungjoo.ham@samsung.com>
Acked-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
parent a296cb5c
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+51 −0
Original line number Diff line number Diff line
@@ -53,6 +53,57 @@ Optional properties only for parent bus device:
- exynos,voltage-tolerance: the percentage value for bus voltage tolerance
			which is used to calculate the max voltage.

Detailed correlation between sub-blocks and power line according to Exynos SoC:
- In case of Exynos3250, there are two power line as following:
	VDD_MIF |--- DMC

	VDD_INT |--- LEFTBUS (parent device)
		|--- PERIL
		|--- MFC
		|--- G3D
		|--- RIGHTBUS
		|--- PERIR
		|--- FSYS
		|--- LCD0
		|--- PERIR
		|--- ISP
		|--- CAM

- In case of Exynos4210, there is one power line as following:
	VDD_INT |--- DMC (parent device)
		|--- LEFTBUS
		|--- PERIL
		|--- MFC(L)
		|--- G3D
		|--- TV
		|--- LCD0
		|--- RIGHTBUS
		|--- PERIR
		|--- MFC(R)
		|--- CAM
		|--- FSYS
		|--- GPS
		|--- LCD0
		|--- LCD1

- In case of Exynos4x12, there are two power line as following:
	VDD_MIF |--- DMC

	VDD_INT |--- LEFTBUS (parent device)
		|--- PERIL
		|--- MFC(L)
		|--- G3D
		|--- TV
		|--- IMAGE
		|--- RIGHTBUS
		|--- PERIR
		|--- MFC(R)
		|--- CAM
		|--- FSYS
		|--- GPS
		|--- LCD0
		|--- ISP

Example1:
	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
	power line (regulator). The MIF (Memory Interface) AXI bus is used to