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Commit b9bd0dc0 authored by Mohammed Javid's avatar Mohammed Javid
Browse files

ARM: dts: msm: Fix ab/ib values for snoc from IPA for sdxpoorwiils 



Voting for SVS2 from IPA towards DDR bumps up SNOC
frequency. Make a change to split the vote from IPA
to MEMNOC and MEMNOC to DDR.

Change-Id: I712b782a56180d71cf448974cead1754f4ee835e
Signed-off-by: default avatarMohammed Javid <mjavid@codeaurora.org>
parent eddc683b

arch/arm/boot/dts/qcom/sdxpoorwills.dtsi

+32 −21
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/regulator/qcom,rpmh-regulator.h>

#include <dt-bindings/clock/qcom,aop-qmp.h>

#include <dt-bindings/msm/msm-bus-ids.h>



#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
@@ -925,33 +926,43 @@ 
		qcom,bandwidth-vote-for-ipa;

		qcom,msm-bus,name = "ipa";

		qcom,msm-bus,num-cases = <5>;

		qcom,msm-bus,num-paths = <4>;

		qcom,msm-bus,num-paths = <5>;

		qcom,msm-bus,vectors-KBps =

		/* No vote */

			<90 512 0 0>,

			<90 585 0 0>,

			<1 676 0 0>,

			<143 777 0 0>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_SNOC_MEM_NOC_GC 0 0>,

		<MSM_BUS_MASTER_SNOC_GC_MEM_NOC MSM_BUS_SLAVE_EBI_CH0 0 0>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 0>,



		/* SVS2 */

			<90 512 900000 1800000>,

			<90 585 300000 600000>,

			<1 676 90000 179000>, /*gcc_config_noc_clk_src */

			<143 777 0 120>, /* IB defined for IPA2X_clk in MHz*/

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_SNOC_MEM_NOC_GC 240000 480000>,

		<MSM_BUS_MASTER_SNOC_GC_MEM_NOC MSM_BUS_SLAVE_EBI_CH0 900000 1800000>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 300000 600000>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 90000 179000>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 120>,



		/* SVS */

			<90 512 1530000 3060000>,

			<90 585 400000 800000>,

			<1 676 100000 199000>,

			<143 777 0 250>, /* IB defined for IPA2X_clk in MHz*/

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_SNOC_MEM_NOC_GC 360000 720000>,

		<MSM_BUS_MASTER_SNOC_GC_MEM_NOC MSM_BUS_SLAVE_EBI_CH0 1530000 3060000>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 400000 800000>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 100000 199000>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 250>,



		/* NOMINAL */

			<90 512 2592000 5184000>,

			<90 585 800000 1600000>,

			<1 676 200000 399000>,

			<143 777 0 440>, /* IB defined for IPA2X_clk in MHz*/

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_SNOC_MEM_NOC_GC 780000 1560000>,

		<MSM_BUS_MASTER_SNOC_GC_MEM_NOC MSM_BUS_SLAVE_EBI_CH0 2592000 5184000>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 800000 1600000>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 200000 399000>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 440>,



		/* TURBO */

			<90 512 2592000 5184000>,

			<90 585 960000 1920000>,

			<1 676 266000 531000>,

			<143 777 0 500>; /* IB defined for IPA clk in MHz*/

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_SNOC_MEM_NOC_GC 960000 1920000>,

		<MSM_BUS_MASTER_SNOC_GC_MEM_NOC MSM_BUS_SLAVE_EBI_CH0 2592000 5184000>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 960000 1920000>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 266000 531000>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 500>;



		qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",

		"TURBO";

		qcom,throughput-threshold = <310 600 1000>;