Loading drivers/platform/msm/mhi_dev/mhi.c +3 −1 Original line number Diff line number Diff line Loading @@ -2403,8 +2403,10 @@ static void mhi_dev_enable(struct work_struct *work) return; } if (mhi_ctx->config_iatu || mhi_ctx->mhi_int) if (mhi_ctx->config_iatu || mhi_ctx->mhi_int) { mhi_ctx->mhi_int_en = true; enable_irq(mhi_ctx->mhi_irq); } mhi_update_state_info(MHI_DEV_UEVENT_CTRL, MHI_STATE_CONFIGURED); } Loading drivers/platform/msm/mhi_dev/mhi.h +2 −0 Original line number Diff line number Diff line Loading @@ -605,6 +605,8 @@ struct mhi_dev { /*Register for interrupt */ bool mhi_int; bool mhi_int_en; /* Registered client callback list */ struct list_head client_cb_list; Loading drivers/platform/msm/mhi_dev/mhi_sm.c +31 −0 Original line number Diff line number Diff line Loading @@ -19,6 +19,7 @@ #include <linux/ipa_mhi.h> #include "mhi_hwio.h" #include "mhi_sm.h" #include <linux/interrupt.h> #define MHI_SM_DBG(fmt, args...) \ mhi_log(MHI_MSG_DBG, fmt, ##args) Loading Loading @@ -775,6 +776,7 @@ static void mhi_sm_pcie_event_manager(struct work_struct *work) struct mhi_sm_ep_pcie_event *chg_event = container_of(work, struct mhi_sm_ep_pcie_event, work); enum ep_pcie_event pcie_event = chg_event->event; unsigned long flags; MHI_SM_FUNC_ENTRY(); Loading Loading @@ -846,6 +848,15 @@ static void mhi_sm_pcie_event_manager(struct work_struct *work) mhi_dev_restore_mmio(mhi_sm_ctx->mhi_dev); spin_lock_irqsave(&mhi_sm_ctx->mhi_dev->lock, flags); if ((mhi_sm_ctx->mhi_dev->mhi_int) && (!mhi_sm_ctx->mhi_dev->mhi_int_en)) { enable_irq(mhi_sm_ctx->mhi_dev->mhi_irq); mhi_sm_ctx->mhi_dev->mhi_int_en = true; MHI_SM_DBG("Enable MHI IRQ during PCIe DEAST"); } spin_unlock_irqrestore(&mhi_sm_ctx->mhi_dev->lock, flags); res = ep_pcie_enable_endpoint(mhi_sm_ctx->mhi_dev->phandle, EP_PCIE_OPT_ENUM); if (res) { Loading Loading @@ -1141,6 +1152,7 @@ void mhi_dev_sm_pcie_handler(struct ep_pcie_notify *notify) { struct mhi_sm_ep_pcie_event *dstate_change_evt; enum ep_pcie_event event; unsigned long flags; MHI_SM_FUNC_ENTRY(); Loading Loading @@ -1173,6 +1185,16 @@ void mhi_dev_sm_pcie_handler(struct ep_pcie_notify *notify) break; case EP_PCIE_EVENT_PM_D3_HOT: mhi_sm_ctx->stats.d3_hot_event_cnt++; spin_lock_irqsave(&mhi_sm_ctx->mhi_dev->lock, flags); if ((mhi_sm_ctx->mhi_dev->mhi_int) && (mhi_sm_ctx->mhi_dev->mhi_int_en)) { disable_irq(mhi_sm_ctx->mhi_dev->mhi_irq); mhi_sm_ctx->mhi_dev->mhi_int_en = false; MHI_SM_DBG("Disable MHI IRQ during D3 HOT"); } spin_unlock_irqrestore(&mhi_sm_ctx->mhi_dev->lock, flags); mhi_dev_backup_mmio(mhi_sm_ctx->mhi_dev); break; case EP_PCIE_EVENT_PM_RST_DEAST: Loading @@ -1180,6 +1202,15 @@ void mhi_dev_sm_pcie_handler(struct ep_pcie_notify *notify) break; case EP_PCIE_EVENT_PM_D0: mhi_sm_ctx->stats.d0_event_cnt++; spin_lock_irqsave(&mhi_sm_ctx->mhi_dev->lock, flags); if ((mhi_sm_ctx->mhi_dev->mhi_int) && (!mhi_sm_ctx->mhi_dev->mhi_int_en)) { enable_irq(mhi_sm_ctx->mhi_dev->mhi_irq); mhi_sm_ctx->mhi_dev->mhi_int_en = true; MHI_SM_DBG("Enable MHI IRQ during D0"); } spin_unlock_irqrestore(&mhi_sm_ctx->mhi_dev->lock, flags); break; case EP_PCIE_EVENT_LINKDOWN: mhi_sm_ctx->stats.linkdown_event_cnt++; Loading Loading
drivers/platform/msm/mhi_dev/mhi.c +3 −1 Original line number Diff line number Diff line Loading @@ -2403,8 +2403,10 @@ static void mhi_dev_enable(struct work_struct *work) return; } if (mhi_ctx->config_iatu || mhi_ctx->mhi_int) if (mhi_ctx->config_iatu || mhi_ctx->mhi_int) { mhi_ctx->mhi_int_en = true; enable_irq(mhi_ctx->mhi_irq); } mhi_update_state_info(MHI_DEV_UEVENT_CTRL, MHI_STATE_CONFIGURED); } Loading
drivers/platform/msm/mhi_dev/mhi.h +2 −0 Original line number Diff line number Diff line Loading @@ -605,6 +605,8 @@ struct mhi_dev { /*Register for interrupt */ bool mhi_int; bool mhi_int_en; /* Registered client callback list */ struct list_head client_cb_list; Loading
drivers/platform/msm/mhi_dev/mhi_sm.c +31 −0 Original line number Diff line number Diff line Loading @@ -19,6 +19,7 @@ #include <linux/ipa_mhi.h> #include "mhi_hwio.h" #include "mhi_sm.h" #include <linux/interrupt.h> #define MHI_SM_DBG(fmt, args...) \ mhi_log(MHI_MSG_DBG, fmt, ##args) Loading Loading @@ -775,6 +776,7 @@ static void mhi_sm_pcie_event_manager(struct work_struct *work) struct mhi_sm_ep_pcie_event *chg_event = container_of(work, struct mhi_sm_ep_pcie_event, work); enum ep_pcie_event pcie_event = chg_event->event; unsigned long flags; MHI_SM_FUNC_ENTRY(); Loading Loading @@ -846,6 +848,15 @@ static void mhi_sm_pcie_event_manager(struct work_struct *work) mhi_dev_restore_mmio(mhi_sm_ctx->mhi_dev); spin_lock_irqsave(&mhi_sm_ctx->mhi_dev->lock, flags); if ((mhi_sm_ctx->mhi_dev->mhi_int) && (!mhi_sm_ctx->mhi_dev->mhi_int_en)) { enable_irq(mhi_sm_ctx->mhi_dev->mhi_irq); mhi_sm_ctx->mhi_dev->mhi_int_en = true; MHI_SM_DBG("Enable MHI IRQ during PCIe DEAST"); } spin_unlock_irqrestore(&mhi_sm_ctx->mhi_dev->lock, flags); res = ep_pcie_enable_endpoint(mhi_sm_ctx->mhi_dev->phandle, EP_PCIE_OPT_ENUM); if (res) { Loading Loading @@ -1141,6 +1152,7 @@ void mhi_dev_sm_pcie_handler(struct ep_pcie_notify *notify) { struct mhi_sm_ep_pcie_event *dstate_change_evt; enum ep_pcie_event event; unsigned long flags; MHI_SM_FUNC_ENTRY(); Loading Loading @@ -1173,6 +1185,16 @@ void mhi_dev_sm_pcie_handler(struct ep_pcie_notify *notify) break; case EP_PCIE_EVENT_PM_D3_HOT: mhi_sm_ctx->stats.d3_hot_event_cnt++; spin_lock_irqsave(&mhi_sm_ctx->mhi_dev->lock, flags); if ((mhi_sm_ctx->mhi_dev->mhi_int) && (mhi_sm_ctx->mhi_dev->mhi_int_en)) { disable_irq(mhi_sm_ctx->mhi_dev->mhi_irq); mhi_sm_ctx->mhi_dev->mhi_int_en = false; MHI_SM_DBG("Disable MHI IRQ during D3 HOT"); } spin_unlock_irqrestore(&mhi_sm_ctx->mhi_dev->lock, flags); mhi_dev_backup_mmio(mhi_sm_ctx->mhi_dev); break; case EP_PCIE_EVENT_PM_RST_DEAST: Loading @@ -1180,6 +1202,15 @@ void mhi_dev_sm_pcie_handler(struct ep_pcie_notify *notify) break; case EP_PCIE_EVENT_PM_D0: mhi_sm_ctx->stats.d0_event_cnt++; spin_lock_irqsave(&mhi_sm_ctx->mhi_dev->lock, flags); if ((mhi_sm_ctx->mhi_dev->mhi_int) && (!mhi_sm_ctx->mhi_dev->mhi_int_en)) { enable_irq(mhi_sm_ctx->mhi_dev->mhi_irq); mhi_sm_ctx->mhi_dev->mhi_int_en = true; MHI_SM_DBG("Enable MHI IRQ during D0"); } spin_unlock_irqrestore(&mhi_sm_ctx->mhi_dev->lock, flags); break; case EP_PCIE_EVENT_LINKDOWN: mhi_sm_ctx->stats.linkdown_event_cnt++; Loading