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Commit b9524a1e authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: remap l3 on hw init 



If any l3 rows have been previously remapped, we must remap them after
GPU reset/resume too.

v2: Just return (no warn) on remapping init if not IVB (Jesse)
Move the check of schizo userspace to i915_gem_l3_remap (Jesse)

Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 15b9f80e

drivers/gpu/drm/i915/i915_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -656,6 +656,8 @@ typedef struct drm_i915_private { 
		/** PPGTT used for aliasing the PPGTT with the GTT */

		struct i915_hw_ppgtt *aliasing_ppgtt;



		u32 *l3_remap_info;



		struct shrinker inactive_shrinker;



		/**
@@ -1309,6 +1311,7 @@ int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, 
int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);

int __must_check i915_gem_init(struct drm_device *dev);

int __must_check i915_gem_init_hw(struct drm_device *dev);

void i915_gem_l3_remap(struct drm_device *dev);

void i915_gem_init_swizzling(struct drm_device *dev);

void i915_gem_init_ppgtt(struct drm_device *dev);

void i915_gem_cleanup_ringbuffer(struct drm_device *dev);

drivers/gpu/drm/i915/i915_gem.c

+34 −0
Original line number Diff line number Diff line
@@ -3527,6 +3527,38 @@ i915_gem_idle(struct drm_device *dev) 
	return 0;

}



void i915_gem_l3_remap(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;

	u32 misccpctl;

	int i;



	if (!IS_IVYBRIDGE(dev))

		return;



	if (!dev_priv->mm.l3_remap_info)

		return;



	misccpctl = I915_READ(GEN7_MISCCPCTL);

	I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);

	POSTING_READ(GEN7_MISCCPCTL);



	for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {

		u32 remap = I915_READ(GEN7_L3LOG_BASE + i);

		if (remap && remap != dev_priv->mm.l3_remap_info[i/4])

			DRM_DEBUG("0x%x was already programmed to %x\n",

				  GEN7_L3LOG_BASE + i, remap);

		if (remap && !dev_priv->mm.l3_remap_info[i/4])

			DRM_DEBUG_DRIVER("Clearing remapped register\n");

		I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]);

	}



	/* Make sure all the writes land before disabling dop clock gating */

	POSTING_READ(GEN7_L3LOG_BASE);



	I915_WRITE(GEN7_MISCCPCTL, misccpctl);

}



void i915_gem_init_swizzling(struct drm_device *dev)

{

	drm_i915_private_t *dev_priv = dev->dev_private;
@@ -3616,6 +3648,8 @@ i915_gem_init_hw(struct drm_device *dev) 
	drm_i915_private_t *dev_priv = dev->dev_private;

	int ret;



	i915_gem_l3_remap(dev);



	i915_gem_init_swizzling(dev);



	ret = intel_init_render_ring_buffer(dev);

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -4111,6 +4111,9 @@ 
		((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)

#define   GEN7_L3CDERRST1_ENABLE	(1<<7)



#define GEN7_L3LOG_BASE			0xB070

#define GEN7_L3LOG_SIZE			0x80



#define G4X_AUD_VID_DID			0x62020

#define INTEL_AUDIO_DEVCL		0x808629FB

#define INTEL_AUDIO_DEVBLC		0x80862801