Loading drivers/gpu/msm/a6xx_reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -816,6 +816,7 @@ #define A6XX_GMU_DCVS_PERF_SETTING 0x1CBFD #define A6XX_GMU_DCVS_BW_SETTING 0x1CBFE #define A6XX_GMU_DCVS_RETURN 0x1CBFF #define A6XX_GMU_SYS_BUS_CONFIG 0x1F40F #define A6XX_GMU_CM3_SYSRESET 0x1F800 #define A6XX_GMU_CM3_BOOT_CONFIG 0x1F801 #define A6XX_GMU_CM3_FW_BUSY 0x1F81A Loading drivers/gpu/msm/adreno_a6xx.c +3 −0 Original line number Diff line number Diff line Loading @@ -904,6 +904,9 @@ static void a6xx_gmu_power_config(struct kgsl_device *device) /* Configure registers for idle setting. The setting is cumulative */ /* Disable GMU WB/RB buffer */ kgsl_gmu_regwrite(device, A6XX_GMU_SYS_BUS_CONFIG, 0x1); kgsl_gmu_regwrite(device, A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9C40400); Loading Loading
drivers/gpu/msm/a6xx_reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -816,6 +816,7 @@ #define A6XX_GMU_DCVS_PERF_SETTING 0x1CBFD #define A6XX_GMU_DCVS_BW_SETTING 0x1CBFE #define A6XX_GMU_DCVS_RETURN 0x1CBFF #define A6XX_GMU_SYS_BUS_CONFIG 0x1F40F #define A6XX_GMU_CM3_SYSRESET 0x1F800 #define A6XX_GMU_CM3_BOOT_CONFIG 0x1F801 #define A6XX_GMU_CM3_FW_BUSY 0x1F81A Loading
drivers/gpu/msm/adreno_a6xx.c +3 −0 Original line number Diff line number Diff line Loading @@ -904,6 +904,9 @@ static void a6xx_gmu_power_config(struct kgsl_device *device) /* Configure registers for idle setting. The setting is cumulative */ /* Disable GMU WB/RB buffer */ kgsl_gmu_regwrite(device, A6XX_GMU_SYS_BUS_CONFIG, 0x1); kgsl_gmu_regwrite(device, A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9C40400); Loading