Loading drivers/gpu/msm/adreno_a6xx.c +4 −4 Original line number Diff line number Diff line Loading @@ -64,10 +64,10 @@ static const struct kgsl_hwcg_reg a630_hwcg_regs[] = { {A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, {A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220}, {A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220}, {A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220}, {A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, {A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, {A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, {A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, {A6XX_RBBM_CLOCK_DELAY_SP0, 0x0000F3CF}, {A6XX_RBBM_CLOCK_DELAY_SP1, 0x0000F3CF}, {A6XX_RBBM_CLOCK_DELAY_SP2, 0x0000F3CF}, Loading Loading
drivers/gpu/msm/adreno_a6xx.c +4 −4 Original line number Diff line number Diff line Loading @@ -64,10 +64,10 @@ static const struct kgsl_hwcg_reg a630_hwcg_regs[] = { {A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222}, {A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, {A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02222220}, {A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02222220}, {A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02222220}, {A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, {A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, {A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, {A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, {A6XX_RBBM_CLOCK_DELAY_SP0, 0x0000F3CF}, {A6XX_RBBM_CLOCK_DELAY_SP1, 0x0000F3CF}, {A6XX_RBBM_CLOCK_DELAY_SP2, 0x0000F3CF}, Loading