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Commit b0e7a85a authored by Duc Dang's avatar Duc Dang
Browse files

arm64: dts: X-Gene: Do not reset or enable/disable clock for AHB block 



Remove register information used to reset and enable/disable clock
for AHB block as reseting AHB or disabling its clock will make other
peripherals attached to it stop working.

Signed-off-by: default avatarDuc Dang <dhdang@apm.com>
parent 0ae8c000

arch/arm64/boot/dts/apm/apm-shadowcat.dtsi

+3 −8
Original line number Diff line number Diff line
@@ -140,17 +140,12 @@ 
				clock-output-names = "socplldiv2";

			};



			ahbclk: ahbclk@1f2ac000 {

			ahbclk: ahbclk@17000000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f2ac000 0x0 0x1000

					0x0 0x17000000 0x0 0x2000>;

				reg-names = "csr-reg", "div-reg";

				csr-offset = <0x0>;

				csr-mask = <0x1>;

				enable-offset = <0x8>;

				enable-mask = <0x1>;

				reg = <0x0 0x17000000 0x0 0x2000>;

				reg-names = "div-reg";

				divider-offset = <0x164>;

				divider-width = <0x5>;

				divider-shift = <0x0>;

arch/arm64/boot/dts/apm/apm-storm.dtsi

+3 −8
Original line number Diff line number Diff line
@@ -150,17 +150,12 @@ 
				clock-output-names = "socplldiv2";

			};



			ahbclk: ahbclk@1f2ac000 {

			ahbclk: ahbclk@17000000 {

				compatible = "apm,xgene-device-clock";

				#clock-cells = <1>;

				clocks = <&socplldiv2 0>;

				reg = <0x0 0x1f2ac000 0x0 0x1000

					0x0 0x17000000 0x0 0x2000>;

				reg-names = "csr-reg", "div-reg";

				csr-offset = <0x0>;

				csr-mask = <0x1>;

				enable-offset = <0x8>;

				enable-mask = <0x1>;

				reg = <0x0 0x17000000 0x0 0x2000>;

				reg-names = "div-reg";

				divider-offset = <0x164>;

				divider-width = <0x5>;

				divider-shift = <0x0>;