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Commit afe2a79d authored by Subhash Jadavani's avatar Subhash Jadavani
Browse files

ARM: dts: msm: add UFS device reset for SDM845 



This change adds pinctrl support for UFS device reset.

Change-Id: I1f1d4c5eb4bad57f0253436095582934d9eec36b
Signed-off-by: default avatarSubhash Jadavani <subhashj@codeaurora.org>
parent 63705c41

arch/arm64/boot/dts/qcom/sdm845-pinctrl.dtsi

+47 −0
Original line number Diff line number Diff line
@@ -20,6 +20,53 @@ 
		interrupt-controller;

		#interrupt-cells = <2>;



		ufs_dev_reset_assert: ufs_dev_reset_assert {

			config {

				pins = "ufs_reset";

				bias-pull-down;		/* default: pull down */

				/*

				 * UFS_RESET driver strengths are having

				 * different values/steps compared to typical

				 * GPIO drive strengths.

				 *

				 * Following table clarifies:

				 *

				 * HDRV value | UFS_RESET | Typical GPIO

				 *   (dec)    |   (mA)    |    (mA)

				 *     0      |   0.8     |    2

				 *     1      |   1.55    |    4

				 *     2      |   2.35    |    6

				 *     3      |   3.1     |    8

				 *     4      |   3.9     |    10

				 *     5      |   4.65    |    12

				 *     6      |   5.4     |    14

				 *     7      |   6.15    |    16

				 *

				 * POR value for UFS_RESET HDRV is 3 which means

				 * 3.1mA and we want to use that. Hence just

				 * specify 8mA to "drive-strength" binding and

				 * that should result into writing 3 to HDRV

				 * field.

				 */

				drive-strength = <8>;	/* default: 3.1 mA */

				output-low; /* active low reset */

			};

		};



		ufs_dev_reset_deassert: ufs_dev_reset_deassert {

			config {

				pins = "ufs_reset";

				bias-pull-down;		/* default: pull down */

				/*

				 * default: 3.1 mA

				 * check comments under ufs_dev_reset_assert

				 */

				drive-strength = <8>;

				output-high; /* active low reset */

			};

		};





		wcd9xxx_intr {

			wcd_intr_default: wcd_intr_default{

				mux {

arch/arm64/boot/dts/qcom/sdm845.dtsi

+3 −1
Original line number Diff line number Diff line
@@ -995,7 +995,9 @@ 
		qcom,pm-qos-cpu-group-latency-us = <70 70>;

		qcom,pm-qos-default-cpu = <0>;



		/* TODO: add UFS device reset support*/

		pinctrl-names = "dev-reset-assert", "dev-reset-deassert";

		pinctrl-0 = <&ufs_dev_reset_assert>;

		pinctrl-1 = <&ufs_dev_reset_deassert>;



		resets = <&clock_gcc GCC_UFS_PHY_BCR>;

		reset-names = "core_reset";