Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit afc641f7 authored by Linux Build Service Account's avatar Linux Build Service Account
Browse files

Merge 8b646d19 on remote branch 

Change-Id: I493980715ee543ef90df55a791e5f979c54a0d37
parents c92eaf63 8b646d19

Documentation/devicetree/bindings/media/video/msm-csi-phy.txt

+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ Required properties: 
    - "qcom,csiphy-v3.1.1"

    - "qcom,csiphy-v3.2"

    - "qcom,csiphy-v3.4.2"

    - "qcom,csiphy-v3.4.2.1"

    - "qcom,csiphy-v3.5"

    - "qcom,csiphy-v5.0"

    - "qcom,csiphy-v5.01"

arch/arm64/boot/dts/qcom/msm-arm-smmu-sdm845.dtsi

+13 −5
Original line number Diff line number Diff line
@@ -346,11 +346,19 @@ 
};



&apps_smmu {

	qcom,actlr =

		/* HF and SF TBUs: +3 deep PF */

			<0x0800 0x7ff 0x103>,

			<0x1000 0x3ff 0x103>;



	qcom,actlr =	<0x0880 0x8 0x103>,

			<0x0881 0x8 0x103>,

			<0x0c80 0x8 0x103>,

			<0x0c81 0x8 0x103>,

			<0x1090 0x0 0x103>,

			<0x1091 0x0 0x103>,

			<0x10a0 0x8 0x103>,

			<0x10b0 0x0 0x103>,

			<0x10a1 0x8 0x103>,

			<0x10a3 0x8 0x103>,

			<0x10a4 0x8 0x103>,

			<0x10b4 0x0 0x103>,

			<0x10a5 0x8 0x103>;

	qcom,mmu500-errata-1 =	<0x800 0x3ff>,

				<0xc00 0x3ff>;

};

arch/arm64/boot/dts/qcom/msm8917-pinctrl.dtsi

+43 −0
Original line number Diff line number Diff line
@@ -1195,6 +1195,49 @@ 
			};

		};



		fpc_reset_int {

			fpc_reset_low: reset_low {

				mux {

					pins = "gpio124";

					function = "fpc_reset_gpio_low";

				};



				config {

					pins = "gpio124";

					drive-strength = <2>;

					bias-disable;

					output-low;

				};

			};



			fpc_reset_high: reset_high {

				mux {

					pins = "gpio124";

					function = "fpc_reset_gpio_high";

				};



				config {

					pins = "gpio124";

					drive-strength = <2>;

					bias-disable;

					output-high;

				};

			};



			fpc_int_low: int_low {

				mux {

					pins = "gpio48";

				};

				config {

					pins = "gpio48";

					drive-strength = <2>;

					bias-pull-down;

					input-enable;

				};

			};

		};





		i2c_2 {

			i2c_2_active: i2c_2_active {

				/* active state */

arch/arm64/boot/dts/qcom/msm8940.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -665,3 +665,16 @@ 
	qcom,temp1-offset = <0 (-2) (-5) (-3) (-1) (-1) (-1) 0 1 (-1) (-6)>;

	qcom,temp2-offset = <1 1 (-7) 5 4 7 6 2 3 1 7>;

};



/* CAMSS_CPHY */

&soc {

	qcom,csiphy@1b34000 {

		status = "ok";

		compatible = "qcom,csiphy-v3.4.2.1", "qcom,csiphy";

	};



	qcom,csiphy@1b35000 {

		status = "ok";

		compatible = "qcom,csiphy-v3.4.2.1", "qcom,csiphy";

	};

};

arch/arm64/boot/dts/qcom/msm8953-coresight.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -890,6 +890,7 @@ 
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu0";

		cpu = <&CPU0>;

		qcom,cit-save;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -904,6 +905,7 @@ 
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu1";

		cpu = <&CPU1>;

		qcom,cit-save;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -918,6 +920,7 @@ 
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu2";

		cpu = <&CPU2>;

		qcom,cit-save;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -932,6 +935,7 @@ 
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu3";

		cpu = <&CPU3>;

		qcom,cit-save;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -946,6 +950,7 @@ 
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu4";

		cpu = <&CPU4>;

		qcom,cit-save;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -960,6 +965,7 @@ 
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu5";

		cpu = <&CPU5>;

		qcom,cit-save;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -974,6 +980,7 @@ 
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu6";

		cpu = <&CPU6>;

		qcom,cit-save;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;
@@ -988,6 +995,7 @@ 
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu7";

		cpu = <&CPU7>;

		qcom,cit-save;



		clocks = <&clock_gcc clk_qdss_clk>,

			 <&clock_gcc clk_qdss_a_clk>;