Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 8b646d19 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: mdss: add support for 10nm DSI PLL shadow clock"

parents 7ab90f59 a4f5ee3c

drivers/clk/qcom/mdss/mdss-dsi-pll-10nm.c

+592 −28

File changed.

Preview size limit exceeded, changes collapsed.

drivers/clk/qcom/mdss/mdss-pll.h

+12 −12
Original line number Diff line number Diff line 
/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -35,6 +35,8 @@ 
		writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \

			(base) + (offset))



#define upper_8_bit(x) ((((x) >> 2) & 0x100) >> 8)



enum {

	MDSS_DSI_PLL_10NM,

	MDSS_DP_PLL_10NM,
@@ -45,30 +47,23 @@ enum { 
	MDSS_PLL_TARGET_8996,

};



#define DFPS_MAX_NUM_OF_FRAME_RATES 20



struct dfps_panel_info {

	uint32_t enabled;

	uint32_t frame_rate_cnt;

	uint32_t frame_rate[DFPS_MAX_NUM_OF_FRAME_RATES]; /* hz */

};

#define DFPS_MAX_NUM_OF_FRAME_RATES 16



struct dfps_pll_codes {

	uint32_t pll_codes_1;

	uint32_t pll_codes_2;

	uint32_t pll_codes_3;

};



struct dfps_codes_info {

	uint32_t is_valid;

	uint32_t frame_rate;	/* hz */

	uint32_t clk_rate;	/* hz */

	struct dfps_pll_codes pll_codes;

};



struct dfps_info {

	struct dfps_panel_info panel_dfps;

	uint32_t vco_rate_cnt;

	struct dfps_codes_info codes_dfps[DFPS_MAX_NUM_OF_FRAME_RATES];

	void *dfps_fb_base;

};



struct mdss_pll_resources {
@@ -139,7 +134,7 @@ struct mdss_pll_resources { 
	/*

	 * caching the pll trim codes in the case of dynamic refresh

	 */

	int		cache_pll_trim_codes[2];

	int		cache_pll_trim_codes[3];



	/*

	 * for maintaining the status of saving trim codes
@@ -181,6 +176,11 @@ struct mdss_pll_resources { 
	 */

	struct dfps_info *dfps;



	/*

	 * for cases where dfps trigger happens before first

	 * suspend/resume and handoff is not finished.

	 */

	bool dfps_trigger;

};



struct mdss_pll_vco_calc {

include/dt-bindings/clock/mdss-10nm-pll-clk.h

+27 −11
Original line number Diff line number Diff line 


/*

 * Copyright (c) 2017, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -26,16 +26,32 @@ 
#define PCLK_SRC_MUX_0_CLK	7

#define PCLK_SRC_0_CLK		8

#define PCLK_MUX_0_CLK		9

#define VCO_CLK_1		10

#define PLL_OUT_DIV_1_CLK	11

#define BITCLK_SRC_1_CLK	12

#define BYTECLK_SRC_1_CLK	13

#define POST_BIT_DIV_1_CLK	14

#define POST_VCO_DIV_1_CLK	15

#define BYTECLK_MUX_1_CLK	16

#define PCLK_SRC_MUX_1_CLK	17

#define PCLK_SRC_1_CLK		18

#define PCLK_MUX_1_CLK		19

#define SHADOW_VCO_CLK_0		10

#define SHADOW_PLL_OUT_DIV_0_CLK	11

#define SHADOW_BITCLK_SRC_0_CLK		12

#define SHADOW_BYTECLK_SRC_0_CLK	13

#define SHADOW_POST_BIT_DIV_0_CLK	14

#define SHADOW_POST_VCO_DIV_0_CLK	15

#define SHADOW_PCLK_SRC_MUX_0_CLK	16

#define SHADOW_PCLK_SRC_0_CLK		17

#define VCO_CLK_1		18

#define PLL_OUT_DIV_1_CLK	19

#define BITCLK_SRC_1_CLK	20

#define BYTECLK_SRC_1_CLK	21

#define POST_BIT_DIV_1_CLK	22

#define POST_VCO_DIV_1_CLK	23

#define BYTECLK_MUX_1_CLK	24

#define PCLK_SRC_MUX_1_CLK	25

#define PCLK_SRC_1_CLK		26

#define PCLK_MUX_1_CLK		27

#define SHADOW_VCO_CLK_1		28

#define SHADOW_PLL_OUT_DIV_1_CLK	29

#define SHADOW_BITCLK_SRC_1_CLK		30

#define SHADOW_BYTECLK_SRC_1_CLK	31

#define SHADOW_POST_BIT_DIV_1_CLK	32

#define SHADOW_POST_VCO_DIV_1_CLK	33

#define SHADOW_PCLK_SRC_MUX_1_CLK	34

#define SHADOW_PCLK_SRC_1_CLK		35



/* DP PLL clocks */

#define	DP_VCO_CLK	0