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Commit abf80c27 authored by Stephen Warren's avatar Stephen Warren
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ARM: tegra: move serial clock-frequency attr into the Tegra30 dtsi



No Tegra30 Platform is running PLL_P at another rate than 408MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent bf5fcc76
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