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Commit a9633279 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Ralf Baechle
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[MIPS] Alchemy PCI code style cleanup 



Fix 15 errors and 4 warnings given by checkpatch.pl:

- space between the asterisk and variable name;

- space after opening and before closing parentheses;

- leading spaces instead of tabs;

- printk() without KERN_* facility level;

- unnecessary braces for single-statement block;

- line over 80 characters.

In addition to these changes, also do the following:

- combine the nested 'if' statements into one when possible;

- remove needless parentheses;

- add missing and remove excess spaces between operator and its operands;

- fix printk() format specifiers mismatching the argument types;

- put the function's result type and name/parameters on the same line;

- insert missing and remove excess new lines;

- properly indent multi-line expressions;

- make the multi-line comment style consistent with the kernel style elsewhere
  by adding empty first line;

- fix typos, capitalize acronyms, etc. in the comments;

- update MontaVista copyright;

- remove Pete Popov's old email address...

Signed-off-by: default avatarSergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c1dcb14e

arch/mips/pci/fixup-au1000.c

+3 −4
Original line number Diff line number Diff line 
/*

 * BRIEF MODULE DESCRIPTION

 *	Board specific pci fixups.

 *	Board specific PCI fixups.

 *

 * Copyright 2001-2003 MontaVista Software Inc.

 * Author: MontaVista Software, Inc.

 *         	ppopov@mvista.com or source@mvista.com

 * Copyright 2001-2003, 2008 MontaVista Software Inc.

 * Author: MontaVista Software, Inc. <source@mvista.com>

 *

 *  This program is free software; you can redistribute  it and/or modify it

 *  under  the terms of  the GNU General  Public License as published by the

arch/mips/pci/ops-au1000.c

+53 −62
Original line number Diff line number Diff line 
/*

 * BRIEF MODULE DESCRIPTION

 *	Alchemy/AMD Au1x00 PCI support.

 *	Alchemy/AMD Au1xx0 PCI support.

 *

 * Copyright 2001-2003, 2007 MontaVista Software Inc.

 * Author: MontaVista Software, Inc.

 *         	ppopov@mvista.com or source@mvista.com

 * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.

 * Author: MontaVista Software, Inc. <source@mvista.com>

 *

 *  Support for all devices (greater than 16) added by David Gathright.

 *
@@ -28,6 +27,7 @@ 
 *  with this program; if not, write  to the Free Software Foundation, Inc.,

 *  675 Mass Ave, Cambridge, MA 02139, USA.

 */



#include <linux/types.h>

#include <linux/pci.h>

#include <linux/kernel.h>
@@ -38,7 +38,7 @@ 


#undef	DEBUG

#ifdef	DEBUG

#define DBG(x...) printk(x)

#define DBG(x...) printk(KERN_DEBUG x)

#else

#define DBG(x...)

#endif
@@ -46,7 +46,6 @@ 
#define PCI_ACCESS_READ  0

#define PCI_ACCESS_WRITE 1





int (*board_pci_idsel)(unsigned int devsel, int assert);



void mod_wired_entry(int entry, unsigned long entrylo0,
@@ -92,8 +91,7 @@ void __init au1x_pci_cfg_init(void) 
}



static int config_access(unsigned char access_type, struct pci_bus *bus,

			 unsigned int dev_fn, unsigned char where,

			 u32 * data)

			 unsigned int dev_fn, unsigned char where, u32 *data)

{

#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)

	unsigned int device = PCI_SLOT(dev_fn);
@@ -114,30 +112,28 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, 
			Au1500_PCI_STATCMD);

	au_sync_udelay(1);



	/* Allow board vendors to implement their own off-chip idsel.

	/*

	 * Allow board vendors to implement their own off-chip IDSEL.

	 * If it doesn't succeed, may as well bail out at this point.

	 */

	if (board_pci_idsel) {

		if (board_pci_idsel(device, 1) == 0) {

	if (board_pci_idsel && board_pci_idsel(device, 1) == 0) {

		*data = 0xffffffff;

		local_irq_restore(flags);

		return -1;

	}

	}



        /* setup the config window */

        if (bus->number == 0) {

                cfg_base = ((1<<device)<<11);

        } else {

	/* Setup the config window */

	if (bus->number == 0)

		cfg_base = (1 << device) << 11;

	else

		cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);

        }



        /* setup the lower bits of the 36 bit address */

	/* Setup the lower bits of the 36-bit address */

	offset = (function << 8) | (where & ~0x3);

	/* pick up any address that falls below the page mask */

	/* Pick up any address that falls below the page mask */

	offset |= cfg_base & ~PAGE_MASK;



	/* page boundary */

	/* Page boundary */

	cfg_base = cfg_base & PAGE_MASK;



	/*
@@ -153,17 +149,17 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, 
		last_entryLo1 = entryLo1;

	}



	if (access_type == PCI_ACCESS_WRITE) {

	if (access_type == PCI_ACCESS_WRITE)

		au_writel(*data, (int)(pci_cfg_vm->addr + offset));

	} else {

	else

		*data = au_readl((int)(pci_cfg_vm->addr + offset));

	}



	au_sync_udelay(2);



	DBG("cfg_access %d bus->number %d dev %d at %x *data %x conf %x\n",

	DBG("cfg_access %d bus->number %u dev %u at %x *data %x conf %lx\n",

	    access_type, bus->number, device, where, *data, offset);



	/* check master abort */

	/* Check master abort */

	status = au_readl(Au1500_PCI_STATCMD);



	if (status & (1 << 29)) {
@@ -171,20 +167,19 @@ static int config_access(unsigned char access_type, struct pci_bus *bus, 
		error = -1;

		DBG("Au1x Master Abort\n");

	} else if ((status >> 28) & 0xf) {

		DBG("PCI ERR detected: device %d, status %x\n", device, ((status >> 28) & 0xf));

		DBG("PCI ERR detected: device %u, status %lx\n",

		    device, (status >> 28) & 0xf);



		/* clear errors */

		/* Clear errors */

		au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD);



		*data = 0xffffffff;

		error = -1;

	}



	/* Take away the idsel.

	*/

	if (board_pci_idsel) {

	/* Take away the IDSEL. */

	if (board_pci_idsel)

		(void)board_pci_idsel(device, 0);

	}



	local_irq_restore(flags);

	return error;
@@ -206,7 +201,6 @@ static int read_config_byte(struct pci_bus *bus, unsigned int devfn, 
	return ret;

}





static int read_config_word(struct pci_bus *bus, unsigned int devfn,

			    int where, u16 *val)

{
@@ -229,9 +223,8 @@ static int read_config_dword(struct pci_bus *bus, unsigned int devfn, 
	return ret;

}



static int

write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,

		  u8 val)

static int write_config_byte(struct pci_bus *bus, unsigned int devfn,

			     int where, u8 val)

{

	u32 data = 0;
@@ -247,9 +240,8 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, 
	return PCIBIOS_SUCCESSFUL;

}



static int

write_config_word(struct pci_bus *bus, unsigned int devfn, int where,

		  u16 val)

static int write_config_word(struct pci_bus *bus, unsigned int devfn,

			     int where, u16 val)

{

	u32 data = 0;
@@ -262,13 +254,11 @@ write_config_word(struct pci_bus *bus, unsigned int devfn, int where, 
	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))

		return -1;





	return PCIBIOS_SUCCESSFUL;

}



static int

write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,

		   u32 val)

static int write_config_dword(struct pci_bus *bus, unsigned int devfn,

			      int where, u32 val)

{

	if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))

		return -1;
@@ -283,12 +273,14 @@ static int config_read(struct pci_bus *bus, unsigned int devfn, 
	case 1: {

			u8 _val;

			int rc = read_config_byte(bus, devfn, where, &_val);



			*val = _val;

			return rc;

		}

	case 2: {

			u16 _val;

			int rc = read_config_word(bus, devfn, where, &_val);



			*val = _val;

			return rc;

		}
@@ -310,7 +302,6 @@ static int config_write(struct pci_bus *bus, unsigned int devfn, 
	}

}





struct pci_ops au1x_pci_ops = {

	config_read,

	config_write