clk: mdss: shutdown 20nm PHY pll properly to fix power issue

The second DSI PLL is consuming power when it is in reset
state. Configure the needed registers to shutdown the
second DSI PLL properly even though its not been used.
Add these register configurations whenever mdss gdsc
is toggled.

Change-Id: I008bc102795ccb5991bf4b61545c2d672b453392
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>