Loading drivers/gpu/msm/adreno.c +5 −5 Original line number Diff line number Diff line Loading @@ -2377,9 +2377,9 @@ int adreno_soft_reset(struct kgsl_device *device) int ret; if (gpudev->oob_set) { ret = gpudev->oob_set(adreno_dev, OOB_CPINIT_SET_MASK, OOB_CPINIT_CHECK_MASK, OOB_CPINIT_CLEAR_MASK); ret = gpudev->oob_set(adreno_dev, OOB_GPU_SET_MASK, OOB_GPU_CHECK_MASK, OOB_GPU_CLEAR_MASK); if (ret) return ret; } Loading @@ -2403,7 +2403,7 @@ int adreno_soft_reset(struct kgsl_device *device) ret = _soft_reset(adreno_dev); if (ret) { if (gpudev->oob_clear) gpudev->oob_clear(adreno_dev, OOB_CPINIT_CLEAR_MASK); gpudev->oob_clear(adreno_dev, OOB_GPU_CLEAR_MASK); return ret; } Loading Loading @@ -2453,7 +2453,7 @@ int adreno_soft_reset(struct kgsl_device *device) adreno_perfcounter_restore(adreno_dev); if (gpudev->oob_clear) gpudev->oob_clear(adreno_dev, OOB_CPINIT_CLEAR_MASK); gpudev->oob_clear(adreno_dev, OOB_GPU_CLEAR_MASK); return ret; } Loading drivers/gpu/msm/kgsl_gmu.c +14 −37 Original line number Diff line number Diff line Loading @@ -1300,37 +1300,6 @@ static int gmu_disable_gdsc(struct gmu_device *gmu) return -ETIMEDOUT; } static int gmu_fast_boot(struct kgsl_device *device) { int ret; struct adreno_device *adreno_dev = ADRENO_DEVICE(device); struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); struct gmu_device *gmu = &device->gmu; hfi_stop(gmu); clear_bit(GMU_HFI_ON, &gmu->flags); ret = gpudev->rpmh_gpu_pwrctrl(adreno_dev, GMU_FW_START, GMU_RESET, 0); if (ret) return ret; /*FIXME: enabling WD interrupt*/ ret = hfi_start(gmu, GMU_WARM_BOOT); if (ret) return ret; ret = gpudev->oob_set(adreno_dev, OOB_CPINIT_SET_MASK, OOB_CPINIT_CHECK_MASK, OOB_CPINIT_CLEAR_MASK); if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) gpudev->oob_clear(adreno_dev, OOB_BOOT_SLUMBER_CLEAR_MASK); return ret; } static int gmu_suspend(struct kgsl_device *device) { struct adreno_device *adreno_dev = ADRENO_DEVICE(device); Loading Loading @@ -1464,14 +1433,19 @@ int gmu_start(struct kgsl_device *device) /* Send DCVS level prior to reset*/ kgsl_pwrctrl_pwrlevel_change(device, pwr->default_pwrlevel); } else { /* GMU fast boot */ hfi_stop(gmu); ret = gpudev->oob_set(adreno_dev, OOB_CPINIT_SET_MASK, OOB_CPINIT_CHECK_MASK, OOB_CPINIT_CLEAR_MASK); ret = gpudev->rpmh_gpu_pwrctrl(adreno_dev, GMU_FW_START, GMU_RESET, 0); if (ret) goto error_gmu; } else gmu_fast_boot(device); ret = hfi_start(gmu, GMU_WARM_BOOT); if (ret) goto error_gmu; } break; default: break; Loading @@ -1480,6 +1454,9 @@ int gmu_start(struct kgsl_device *device) return ret; error_gmu: if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) gpudev->oob_clear(adreno_dev, OOB_BOOT_SLUMBER_CLEAR_MASK); gmu_snapshot(device); return ret; } Loading drivers/gpu/msm/kgsl_gmu.h +3 −6 Original line number Diff line number Diff line Loading @@ -70,15 +70,12 @@ #define OOB_DCVS_SET_MASK BIT(23) #define OOB_DCVS_CHECK_MASK BIT(31) #define OOB_DCVS_CLEAR_MASK BIT(31) #define OOB_CPINIT_SET_MASK BIT(16) #define OOB_CPINIT_CHECK_MASK BIT(24) #define OOB_CPINIT_CLEAR_MASK BIT(24) #define OOB_GPU_SET_MASK BIT(16) #define OOB_GPU_CHECK_MASK BIT(24) #define OOB_GPU_CLEAR_MASK BIT(24) #define OOB_PERFCNTR_SET_MASK BIT(17) #define OOB_PERFCNTR_CHECK_MASK BIT(25) #define OOB_PERFCNTR_CLEAR_MASK BIT(25) #define OOB_GPU_SET_MASK BIT(18) #define OOB_GPU_CHECK_MASK BIT(26) #define OOB_GPU_CLEAR_MASK BIT(26) /* Bits for the flags field in the gmu structure */ enum gmu_flags { Loading Loading
drivers/gpu/msm/adreno.c +5 −5 Original line number Diff line number Diff line Loading @@ -2377,9 +2377,9 @@ int adreno_soft_reset(struct kgsl_device *device) int ret; if (gpudev->oob_set) { ret = gpudev->oob_set(adreno_dev, OOB_CPINIT_SET_MASK, OOB_CPINIT_CHECK_MASK, OOB_CPINIT_CLEAR_MASK); ret = gpudev->oob_set(adreno_dev, OOB_GPU_SET_MASK, OOB_GPU_CHECK_MASK, OOB_GPU_CLEAR_MASK); if (ret) return ret; } Loading @@ -2403,7 +2403,7 @@ int adreno_soft_reset(struct kgsl_device *device) ret = _soft_reset(adreno_dev); if (ret) { if (gpudev->oob_clear) gpudev->oob_clear(adreno_dev, OOB_CPINIT_CLEAR_MASK); gpudev->oob_clear(adreno_dev, OOB_GPU_CLEAR_MASK); return ret; } Loading Loading @@ -2453,7 +2453,7 @@ int adreno_soft_reset(struct kgsl_device *device) adreno_perfcounter_restore(adreno_dev); if (gpudev->oob_clear) gpudev->oob_clear(adreno_dev, OOB_CPINIT_CLEAR_MASK); gpudev->oob_clear(adreno_dev, OOB_GPU_CLEAR_MASK); return ret; } Loading
drivers/gpu/msm/kgsl_gmu.c +14 −37 Original line number Diff line number Diff line Loading @@ -1300,37 +1300,6 @@ static int gmu_disable_gdsc(struct gmu_device *gmu) return -ETIMEDOUT; } static int gmu_fast_boot(struct kgsl_device *device) { int ret; struct adreno_device *adreno_dev = ADRENO_DEVICE(device); struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); struct gmu_device *gmu = &device->gmu; hfi_stop(gmu); clear_bit(GMU_HFI_ON, &gmu->flags); ret = gpudev->rpmh_gpu_pwrctrl(adreno_dev, GMU_FW_START, GMU_RESET, 0); if (ret) return ret; /*FIXME: enabling WD interrupt*/ ret = hfi_start(gmu, GMU_WARM_BOOT); if (ret) return ret; ret = gpudev->oob_set(adreno_dev, OOB_CPINIT_SET_MASK, OOB_CPINIT_CHECK_MASK, OOB_CPINIT_CLEAR_MASK); if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) gpudev->oob_clear(adreno_dev, OOB_BOOT_SLUMBER_CLEAR_MASK); return ret; } static int gmu_suspend(struct kgsl_device *device) { struct adreno_device *adreno_dev = ADRENO_DEVICE(device); Loading Loading @@ -1464,14 +1433,19 @@ int gmu_start(struct kgsl_device *device) /* Send DCVS level prior to reset*/ kgsl_pwrctrl_pwrlevel_change(device, pwr->default_pwrlevel); } else { /* GMU fast boot */ hfi_stop(gmu); ret = gpudev->oob_set(adreno_dev, OOB_CPINIT_SET_MASK, OOB_CPINIT_CHECK_MASK, OOB_CPINIT_CLEAR_MASK); ret = gpudev->rpmh_gpu_pwrctrl(adreno_dev, GMU_FW_START, GMU_RESET, 0); if (ret) goto error_gmu; } else gmu_fast_boot(device); ret = hfi_start(gmu, GMU_WARM_BOOT); if (ret) goto error_gmu; } break; default: break; Loading @@ -1480,6 +1454,9 @@ int gmu_start(struct kgsl_device *device) return ret; error_gmu: if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) gpudev->oob_clear(adreno_dev, OOB_BOOT_SLUMBER_CLEAR_MASK); gmu_snapshot(device); return ret; } Loading
drivers/gpu/msm/kgsl_gmu.h +3 −6 Original line number Diff line number Diff line Loading @@ -70,15 +70,12 @@ #define OOB_DCVS_SET_MASK BIT(23) #define OOB_DCVS_CHECK_MASK BIT(31) #define OOB_DCVS_CLEAR_MASK BIT(31) #define OOB_CPINIT_SET_MASK BIT(16) #define OOB_CPINIT_CHECK_MASK BIT(24) #define OOB_CPINIT_CLEAR_MASK BIT(24) #define OOB_GPU_SET_MASK BIT(16) #define OOB_GPU_CHECK_MASK BIT(24) #define OOB_GPU_CLEAR_MASK BIT(24) #define OOB_PERFCNTR_SET_MASK BIT(17) #define OOB_PERFCNTR_CHECK_MASK BIT(25) #define OOB_PERFCNTR_CLEAR_MASK BIT(25) #define OOB_GPU_SET_MASK BIT(18) #define OOB_GPU_CHECK_MASK BIT(26) #define OOB_GPU_CLEAR_MASK BIT(26) /* Bits for the flags field in the gmu structure */ enum gmu_flags { Loading