Merge "ARM: dts: msm: Enable SMMU S1 translation for crypto drivers on sdm845" (96d2b552) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/crypto/msm/qcedev.txt

+1 −1

Original line number	Diff line number	Diff line
		@@ -20,7 +20,7 @@ Optional properties:
		- qcom,ce-hw-key : optional, indicates if the hardware supports use of HW KEY.
		- qcom,support-core-clk-only : optional, indicates if the HW supports single crypto core clk.
		- qcom,bsm-ee : optional, indicate the BAM EE value, changes from target to target. Default value is 1 if not specified.
		- qcom,smmu-s1-bypass : Boolean flag to bypass SMMU stage 1 translation.
		- qcom,smmu-s1-enable : Boolean flag to enable SMMU stage 1 translation.
		- iommus : A list of phandle and IOMMU specifier pairs that describe the IOMMU master interfaces of the device.

		Example:

Documentation/devicetree/bindings/crypto/msm/qcrypto.txt

+1 −1

Original line number	Diff line number	Diff line
		@@ -40,7 +40,7 @@ Optional properties:
		required. For other targets such as fsm, they do not perform
		bus scaling. It is not required for those targets.

		- qcom,smmu-s1-bypass : Boolean flag to bypass SMMU stage 1 translation.
		- qcom,smmu-s1-enable : Boolean flag to bypass SMMU stage 1 translation.
		- iommus : A list of phandle and IOMMU specifier pairs that describe the IOMMU master interfaces of the device.

		Example:

arch/arm64/boot/dts/qcom/sdm845.dtsi

+7 −7

Original line number	Diff line number	Diff line
		@@ -2723,7 +2723,7 @@
		<0x1dc4000 0x24000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <0 272 0>;
		qcom,bam-pipe-pair = <1>;
		qcom,bam-pipe-pair = <3>;
		qcom,ce-hw-instance = <0>;
		qcom,ce-device = <0>;
		qcom,ce-hw-shared;
		@@ -2742,9 +2742,9 @@
		<&clock_gcc GCC_CE1_AXI_CLK>;
		qcom,ce-opp-freq = <171430000>;
		qcom,request-bw-before-clk;
		qcom,smmu-s1-bypass;
		iommus = <&apps_smmu 0x702 0x1>,
		<&apps_smmu 0x712 0x1>;
		qcom,smmu-s1-enable;
		iommus = <&apps_smmu 0x706 0x1>,
		<&apps_smmu 0x716 0x1>;
		};

		qcom_msmhdcp: qcom,msm_hdcp {
		@@ -2783,9 +2783,9 @@
		qcom,use-sw-ahash-algo;
		qcom,use-sw-aead-algo;
		qcom,use-sw-hmac-algo;
		qcom,smmu-s1-bypass;
		iommus = <&apps_smmu 0x704 0x3>,
		<&apps_smmu 0x714 0x3>;
		qcom,smmu-s1-enable;
		iommus = <&apps_smmu 0x704 0x1>,
		<&apps_smmu 0x714 0x1>;
		};

		qcom,msm_gsi {

drivers/crypto/msm/qce50.c

+24 −17

Original line number	Diff line number	Diff line
		@@ -162,7 +162,7 @@ struct qce_device {
		bool cadence_flag;
		uint8_t *dummyreq_in_buf;
		struct dma_iommu_mapping *smmu_mapping;
		bool bypass_s1_smmu;
		bool enable_s1_smmu;
		};

		static void print_notify_debug(struct sps_event_notify *notify);
		@@ -5716,8 +5716,8 @@ static int __qce_get_device_tree_data(struct platform_device *pdev,
		pce_dev->ce_opp_freq_hz = CE_CLK_100MHZ;
		}

		if (of_property_read_bool((&pdev->dev)->of_node, "qcom,smmu-s1-bypass"))
		pce_dev->bypass_s1_smmu = true;
		if (of_property_read_bool((&pdev->dev)->of_node, "qcom,smmu-s1-enable"))
		pce_dev->enable_s1_smmu = true;

		pce_dev->ce_bam_info.dest_pipe_index =
		2 * pce_dev->ce_bam_info.pipe_pair_index;
		@@ -5963,7 +5963,7 @@ static void qce_iommu_release_iomapping(struct qce_device *pce_dev)
		static int qce_smmu_init(struct qce_device *pce_dev)
		{
		struct dma_iommu_mapping *mapping;
		int s1_bypass = 1;
		int attr = 1;
		int ret = 0;

		mapping = arm_iommu_create_mapping(&platform_bus_type,
		@@ -5975,9 +5975,16 @@ static int qce_smmu_init(struct qce_device *pce_dev)
		}

		ret = iommu_domain_set_attr(mapping->domain,
		DOMAIN_ATTR_S1_BYPASS, &s1_bypass);
		DOMAIN_ATTR_ATOMIC, &attr);
		if (ret < 0) {
		pr_err("Set s1_bypass attribute failed, err = %d\n", ret);
		pr_err("Set ATOMIC attr failed, err = %d\n", ret);
		goto ext_fail_set_attr;
		}

		ret = iommu_domain_set_attr(mapping->domain,
		DOMAIN_ATTR_UPSTREAM_IOVA_ALLOCATOR, &attr);
		if (ret < 0) {
		pr_err("Set UPSTREAM_IOVA_ALLOCATOR failed, err = %d\n", ret);
		goto ext_fail_set_attr;
		}

		@@ -6020,6 +6027,13 @@ void qce_open(struct platform_device pdev, int *rc)
		goto err_pce_dev;
		}

		if (pce_dev->enable_s1_smmu) {
		if (qce_smmu_init(pce_dev)) {
		*rc = -EIO;
		goto err_pce_dev;
		}
		}

		for (i = 0; i < MAX_QCE_ALLOC_BAM_REQ; i++)
		atomic_set(&pce_dev->ce_request_info[i].in_use, false);
		pce_dev->ce_request_index = 0;
		@@ -6051,13 +6065,6 @@ void qce_open(struct platform_device pdev, int *rc)
		if (*rc)
		goto err_enable_clk;

		if (pce_dev->bypass_s1_smmu) {
		if (qce_smmu_init(pce_dev)) {
		*rc = -EIO;
		goto err_smmu;
		}
		}

		if (_probe_ce_engine(pce_dev)) {
		*rc = -ENXIO;
		goto err;
		@@ -6084,9 +6091,6 @@ void qce_open(struct platform_device pdev, int *rc)
		mutex_unlock(&qce_iomap_mutex);
		return pce_dev;
		err:
		if (pce_dev->bypass_s1_smmu)
		qce_iommu_release_iomapping(pce_dev);
		err_smmu:
		qce_disable_clk(pce_dev);

		err_enable_clk:
		@@ -6099,6 +6103,9 @@ void qce_open(struct platform_device pdev, int *rc)
		dma_free_coherent(pce_dev->pdev, pce_dev->memsize,
		pce_dev->coh_vmem, pce_dev->coh_pmem);
		err_iobase:
		if (pce_dev->enable_s1_smmu)
		qce_iommu_release_iomapping(pce_dev);

		if (pce_dev->iobase)
		iounmap(pce_dev->iobase);
		err_pce_dev:
		@@ -6128,7 +6135,7 @@ int qce_close(void *handle)
		kfree(pce_dev->dummyreq_in_buf);
		kfree(pce_dev->iovec_vmem);

		if (pce_dev->bypass_s1_smmu)
		if (pce_dev->enable_s1_smmu)
		qce_iommu_release_iomapping(pce_dev);

		qce_disable_clk(pce_dev);