Loading arch/arm64/boot/dts/qcom/msm8937.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -53,7 +53,7 @@ }; }; reserved-memory { reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; Loading arch/arm64/boot/dts/qcom/sdm439.dtsi +41 −0 Original line number Diff line number Diff line Loading @@ -87,3 +87,44 @@ >; }; }; &kgsl_smmu { qcom,enable-static-cb; }; &reserved_memory { gpu_mem: gpu_region@0 { compatible = "shared-dma-pool"; reusable; alloc-ranges = <0x0 0x80000000 0x0 0x10000000>; alignment = <0 0x400000>; size = <0 0x800000>; }; }; &soc { pil_gpu: qcom,kgsl-hyp { compatible = "qcom,pil-tz-generic"; qcom,pas-id = <13>; qcom,firmware-name = "a506_zap"; memory-region = <&gpu_mem>; qcom,mas-crypto = <&mas_crypto>; clocks = <&clock_gcc clk_gcc_crypto_clk>, <&clock_gcc clk_gcc_crypto_ahb_clk>, <&clock_gcc clk_gcc_crypto_axi_clk>, <&clock_gcc clk_crypto_clk_src>; clock-names = "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src"; qcom,proxy-clock-names = "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src"; qcom,scm_core_clk_src-freq = <80000000>; }; }; &kgsl_msm_iommu { gfx3d_secure: gfx3d_secure { compatible = "qcom,smmu-kgsl-cb"; iommus = <&kgsl_smmu 2>; memory-region = <&secure_mem>; }; }; Loading
arch/arm64/boot/dts/qcom/msm8937.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -53,7 +53,7 @@ }; }; reserved-memory { reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; Loading
arch/arm64/boot/dts/qcom/sdm439.dtsi +41 −0 Original line number Diff line number Diff line Loading @@ -87,3 +87,44 @@ >; }; }; &kgsl_smmu { qcom,enable-static-cb; }; &reserved_memory { gpu_mem: gpu_region@0 { compatible = "shared-dma-pool"; reusable; alloc-ranges = <0x0 0x80000000 0x0 0x10000000>; alignment = <0 0x400000>; size = <0 0x800000>; }; }; &soc { pil_gpu: qcom,kgsl-hyp { compatible = "qcom,pil-tz-generic"; qcom,pas-id = <13>; qcom,firmware-name = "a506_zap"; memory-region = <&gpu_mem>; qcom,mas-crypto = <&mas_crypto>; clocks = <&clock_gcc clk_gcc_crypto_clk>, <&clock_gcc clk_gcc_crypto_ahb_clk>, <&clock_gcc clk_gcc_crypto_axi_clk>, <&clock_gcc clk_crypto_clk_src>; clock-names = "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src"; qcom,proxy-clock-names = "scm_core_clk", "scm_iface_clk", "scm_bus_clk", "scm_core_clk_src"; qcom,scm_core_clk_src-freq = <80000000>; }; }; &kgsl_msm_iommu { gfx3d_secure: gfx3d_secure { compatible = "qcom,smmu-kgsl-cb"; iommus = <&kgsl_smmu 2>; memory-region = <&secure_mem>; }; };