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Commit a4f792a1 authored by Kyle Yan's avatar Kyle Yan Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: populate block names and lengths in catalog" into msm-4.8

parents 32952371 77158731

Documentation/devicetree/bindings/display/msm/sde.txt

+4 −0
Original line number Diff line number Diff line
@@ -184,6 +184,7 @@ Optional properties: 
				e.g. qcom,sde-sspp-vig-blocks

				-- qcom,sde-vig-csc-off: offset of CSC hardware

				-- qcom,sde-vig-qseed-off: offset of QSEED hardware

				-- qcom,sde-vig-qseed-size: A u32 address range for qseed scaler.

				-- qcom,sde-vig-pcc: offset and version of PCC hardware

				-- qcom,sde-vig-hsic: offset and version of global PA adjustment

				-- qcom,sde-vig-memcolor: offset and version of PA memcolor hardware
@@ -193,6 +194,7 @@ Optional properties: 
				indicates that the SSPP RGB contains that feature hardware.

				e.g. qcom,sde-sspp-vig-blocks

				-- qcom,sde-rgb-scaler-off: offset of RGB scaler hardware

				-- qcom,sde-rgb-scaler-size: A u32 address range for scaler.

				-- qcom,sde-rgb-pcc: offset and version of PCC hardware

- qcom,sde-dspp-blocks:		A node that lists the blocks inside the DSPP hardware. The

				block entries will contain the offset and version of each
@@ -449,6 +451,7 @@ Example: 
    qcom,sde-sspp-vig-blocks {

        qcom,sde-vig-csc-off = <0x320>;

        qcom,sde-vig-qseed-off = <0x200>;

        qcom,sde-vig-qseed-size = <0x74>;

        /* Offset from vig top, version of HSIC */

        qcom,sde-vig-hsic = <0x200 0x00010000>;

        qcom,sde-vig-memcolor = <0x200 0x00010000>;
@@ -457,6 +460,7 @@ Example: 


    qcom,sde-sspp-rgb-blocks {

        qcom,sde-rgb-scaler-off = <0x200>;

        qcom,sde-rgb-scaler-size = <0x74>;

        qcom,sde-rgb-pcc = <0x380 0x00010000>;

    };

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+56 −1
Original line number Diff line number Diff line
@@ -132,6 +132,7 @@ enum { 


enum {

	VIG_QSEED_OFF,

	VIG_QSEED_LEN,

	VIG_CSC_OFF,

	VIG_HSIC_PROP,

	VIG_MEMCOLOR_PROP,
@@ -141,6 +142,7 @@ enum { 


enum {

	RGB_SCALER_OFF,

	RGB_SCALER_LEN,

	RGB_PCC_PROP,

	RGB_PROP_MAX,

};
@@ -316,6 +318,7 @@ static struct sde_prop_type sspp_prop[] = { 


static struct sde_prop_type vig_prop[] = {

	{VIG_QSEED_OFF, "qcom,sde-vig-qseed-off", false, PROP_TYPE_U32},

	{VIG_QSEED_LEN, "qcom,sde-vig-qseed-size", false, PROP_TYPE_U32},

	{VIG_CSC_OFF, "qcom,sde-vig-csc-off", false, PROP_TYPE_U32},

	{VIG_HSIC_PROP, "qcom,sde-vig-hsic", false, PROP_TYPE_U32_ARRAY},

	{VIG_MEMCOLOR_PROP, "qcom,sde-vig-memcolor", false,
@@ -325,6 +328,7 @@ static struct sde_prop_type vig_prop[] = { 


static struct sde_prop_type rgb_prop[] = {

	{RGB_SCALER_OFF, "qcom,sde-rgb-scaler-off", false, PROP_TYPE_U32},

	{RGB_SCALER_LEN, "qcom,sde-rgb-scaler-size", false, PROP_TYPE_U32},

	{RGB_PCC_PROP, "qcom,sde-rgb-pcc", false, PROP_TYPE_U32_ARRAY},

};
@@ -689,6 +693,7 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, 
	sblk->maxupscale = MAX_SSPP_UPSCALE;

	sblk->maxdwnscale = MAX_SSPP_DOWNSCALE;

	sspp->id = SSPP_VIG0 + *vig_count;

	snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u", sspp->id);

	sspp->clk_ctrl = SDE_CLK_CTRL_VIG0 + *vig_count;

	sblk->format_list = plane_formats_yuv;

	set_bit(SDE_SSPP_QOS, &sspp->features);
@@ -702,14 +707,24 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, 
		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED2;

		sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,

			VIG_QSEED_OFF, 0);

		sblk->scaler_blk.len = PROP_VALUE_ACCESS(prop_value,

			VIG_QSEED_LEN, 0);

		snprintf(sblk->scaler_blk.name, SDE_HW_BLK_NAME_LEN,

				"sspp_scaler%u", sspp->id);

	} else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3) {

		set_bit(SDE_SSPP_SCALER_QSEED3, &sspp->features);

		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED3;

		sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,

			VIG_QSEED_OFF, 0);

		sblk->scaler_blk.len = PROP_VALUE_ACCESS(prop_value,

			VIG_QSEED_LEN, 0);

		snprintf(sblk->scaler_blk.name, SDE_HW_BLK_NAME_LEN,

			"sspp_scaler%u", sspp->id);

	}



	sblk->csc_blk.id = SDE_SSPP_CSC;

	snprintf(sblk->csc_blk.name, SDE_HW_BLK_NAME_LEN,

			"sspp_csc%u", sspp->id);

	if (sde_cfg->csc_type == SDE_SSPP_CSC) {

		set_bit(SDE_SSPP_CSC, &sspp->features);

		sblk->csc_blk.base = PROP_VALUE_ACCESS(prop_value,
@@ -721,6 +736,8 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, 
	}



	sblk->hsic_blk.id = SDE_SSPP_HSIC;

	snprintf(sblk->hsic_blk.name, SDE_HW_BLK_NAME_LEN,

			"sspp_hsic%u", sspp->id);

	if (prop_exists[VIG_HSIC_PROP]) {

		sblk->hsic_blk.base = PROP_VALUE_ACCESS(prop_value,

			VIG_HSIC_PROP, 0);
@@ -731,6 +748,8 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, 
	}



	sblk->memcolor_blk.id = SDE_SSPP_MEMCOLOR;

	snprintf(sblk->memcolor_blk.name, SDE_HW_BLK_NAME_LEN,

			"sspp_memcolor%u", sspp->id);

	if (prop_exists[VIG_MEMCOLOR_PROP]) {

		sblk->memcolor_blk.base = PROP_VALUE_ACCESS(prop_value,

			VIG_MEMCOLOR_PROP, 0);
@@ -741,6 +760,8 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, 
	}



	sblk->pcc_blk.id = SDE_SSPP_PCC;

	snprintf(sblk->pcc_blk.name, SDE_HW_BLK_NAME_LEN,

			"sspp_pcc%u", sspp->id);

	if (prop_exists[VIG_PCC_PROP]) {

		sblk->pcc_blk.base = PROP_VALUE_ACCESS(prop_value,

			VIG_PCC_PROP, 0);
@@ -758,6 +779,7 @@ static void _sde_sspp_setup_rgb(struct sde_mdss_cfg *sde_cfg, 
	sblk->maxupscale = MAX_SSPP_UPSCALE;

	sblk->maxdwnscale = MAX_SSPP_DOWNSCALE;

	sspp->id = SSPP_RGB0 + *rgb_count;

	snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u", sspp->id);

	sspp->clk_ctrl = SDE_CLK_CTRL_RGB0 + *rgb_count;

	sblk->format_list = plane_formats;

	set_bit(SDE_SSPP_QOS, &sspp->features);
@@ -771,11 +793,19 @@ static void _sde_sspp_setup_rgb(struct sde_mdss_cfg *sde_cfg, 
		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED2;

		sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,

			RGB_SCALER_OFF, 0);

		sblk->scaler_blk.len = PROP_VALUE_ACCESS(prop_value,

			RGB_SCALER_LEN, 0);

		snprintf(sblk->scaler_blk.name, SDE_HW_BLK_NAME_LEN,

			"sspp_scaler%u", sspp->id);

	} else if (sde_cfg->qseed_type == SDE_SSPP_SCALER_QSEED3) {

		set_bit(SDE_SSPP_SCALER_RGB, &sspp->features);

		sblk->scaler_blk.id = SDE_SSPP_SCALER_QSEED3;

		sblk->scaler_blk.base = PROP_VALUE_ACCESS(prop_value,

			RGB_SCALER_OFF, 0);

			RGB_SCALER_LEN, 0);

		sblk->scaler_blk.len = PROP_VALUE_ACCESS(prop_value,

			SSPP_SCALE_SIZE, 0);

		snprintf(sblk->scaler_blk.name, SDE_HW_BLK_NAME_LEN,

			"sspp_scaler%u", sspp->id);

	}



	sblk->pcc_blk.id = SDE_SSPP_PCC;
@@ -797,6 +827,7 @@ static void _sde_sspp_setup_cursor(struct sde_mdss_cfg *sde_cfg, 
	sblk->maxupscale = SSPP_UNITY_SCALE;

	sblk->maxdwnscale = SSPP_UNITY_SCALE;

	sspp->id = SSPP_CURSOR0 + *cursor_count;

	snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u", sspp->id);

	sspp->clk_ctrl = SDE_CLK_CTRL_CURSOR0 + *cursor_count;

	sblk->format_list = plane_formats;

	(*cursor_count)++;
@@ -810,6 +841,7 @@ static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg, 
	sblk->maxdwnscale = SSPP_UNITY_SCALE;

	sspp->id = SSPP_DMA0 + *dma_count;

	sspp->clk_ctrl = SDE_CLK_CTRL_DMA0 + *dma_count;

	snprintf(sspp->name, SDE_HW_BLK_NAME_LEN, "sspp_%u", sspp->id);

	sblk->format_list = plane_formats;

	set_bit(SDE_SSPP_QOS, &sspp->features);

	(*dma_count)++;
@@ -908,6 +940,7 @@ static int sde_sspp_parse_dt(struct device_node *np, 
		sspp->sblk = sblk;



		sspp->base = PROP_VALUE_ACCESS(prop_value, SSPP_OFF, i);

		sspp->len = PROP_VALUE_ACCESS(prop_value, SSPP_SIZE, 0);

		sblk->maxlinewidth = sde_cfg->max_sspp_linewidth;



		set_bit(SDE_SSPP_SRC, &sspp->features);
@@ -919,6 +952,8 @@ static int sde_sspp_parse_dt(struct device_node *np, 
			set_bit(sde_cfg->smart_dma_rev, &sspp->features);



		sblk->src_blk.id = SDE_SSPP_SRC;

		snprintf(sblk->src_blk.name, SDE_HW_BLK_NAME_LEN, "sspp_src_%u",

				sblk->src_blk.id);



		of_property_read_string_index(np,

				sspp_prop[SSPP_TYPE].prop_name, i, &type);
@@ -1034,7 +1069,9 @@ static int sde_ctl_parse_dt(struct device_node *np, 
	for (i = 0; i < off_count; i++) {

		ctl = sde_cfg->ctl + i;

		ctl->base = PROP_VALUE_ACCESS(prop_value, HW_OFF, i);

		ctl->len = PROP_VALUE_ACCESS(prop_value, HW_LEN, 0);

		ctl->id = CTL_0 + i;

		snprintf(ctl->name, SDE_HW_BLK_NAME_LEN, "ctl_%u", ctl->id);



		if (i < MAX_SPLIT_DISPLAY_CTL)

			set_bit(SDE_CTL_SPLIT_DISPLAY, &ctl->features);
@@ -1145,6 +1182,8 @@ static int sde_mixer_parse_dt(struct device_node *np, 
		mixer->base = PROP_VALUE_ACCESS(prop_value, MIXER_OFF, i);

		mixer->len = PROP_VALUE_ACCESS(prop_value, MIXER_LEN, 0);

		mixer->id = LM_0 + i;

		snprintf(mixer->name, SDE_HW_BLK_NAME_LEN, "lm_%u", mixer->id);



		if (!prop_exists[MIXER_LEN])

			mixer->len = DEFAULT_SDE_HW_BLOCK_LEN;
@@ -1239,6 +1278,8 @@ static int sde_intf_parse_dt(struct device_node *np, 
		intf->base = PROP_VALUE_ACCESS(prop_value, INTF_OFF, i);

		intf->len = PROP_VALUE_ACCESS(prop_value, INTF_LEN, 0);

		intf->id = INTF_0 + i;

		snprintf(intf->name, SDE_HW_BLK_NAME_LEN, "intf_%u", intf->id);



		if (!prop_exists[INTF_LEN])

			intf->len = DEFAULT_SDE_HW_BLOCK_LEN;
@@ -1317,6 +1358,7 @@ static int sde_wb_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg) 


		wb->base = PROP_VALUE_ACCESS(prop_value, WB_OFF, i);

		wb->id = WB_0 + PROP_VALUE_ACCESS(prop_value, WB_ID, i);

		snprintf(wb->name, SDE_HW_BLK_NAME_LEN, "wb_%u", wb->id);

		wb->clk_ctrl = SDE_CLK_CTRL_WB0 +

			PROP_VALUE_ACCESS(prop_value, WB_ID, i);

		wb->xin_id = PROP_VALUE_ACCESS(prop_value, WB_XIN_ID, i);
@@ -1542,7 +1584,9 @@ static int sde_dspp_parse_dt(struct device_node *np, 
	for (i = 0; i < off_count; i++) {

		dspp = sde_cfg->dspp + i;

		dspp->base = PROP_VALUE_ACCESS(prop_value, DSPP_OFF, i);

		dspp->len = PROP_VALUE_ACCESS(prop_value, DSPP_SIZE, 0);

		dspp->id = DSPP_0 + i;

		snprintf(dspp->name, SDE_HW_BLK_NAME_LEN, "dspp_%u", dspp->id);



		sblk = kzalloc(sizeof(*sblk), GFP_KERNEL);

		if (!sblk) {
@@ -1612,6 +1656,7 @@ static int sde_cdm_parse_dt(struct device_node *np, 
		cdm = sde_cfg->cdm + i;

		cdm->base = PROP_VALUE_ACCESS(prop_value, HW_OFF, i);

		cdm->id = CDM_0 + i;

		snprintf(cdm->name, SDE_HW_BLK_NAME_LEN, "cdm_%u", cdm->id);

		cdm->len = PROP_VALUE_ACCESS(prop_value, HW_LEN, 0);



		/* intf3 and wb2 for cdm block */
@@ -1803,15 +1848,19 @@ static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg) 


		pp->base = PROP_VALUE_ACCESS(prop_value, PP_OFF, i);

		pp->id = PINGPONG_0 + i;

		snprintf(pp->name, SDE_HW_BLK_NAME_LEN, "pingpong_%u", pp->id);

		pp->len = PROP_VALUE_ACCESS(prop_value, PP_LEN, 0);



		sblk->te.base = PROP_VALUE_ACCESS(prop_value, TE_OFF, i);

		sblk->te.id = SDE_PINGPONG_TE;

		snprintf(sblk->te.name, SDE_HW_BLK_NAME_LEN, "te_%u", pp->id);

		set_bit(SDE_PINGPONG_TE, &pp->features);



		sblk->te2.base = PROP_VALUE_ACCESS(prop_value, TE2_OFF, i);

		if (sblk->te2.base) {

			sblk->te2.id = SDE_PINGPONG_TE2;

			snprintf(sblk->te2.name, SDE_HW_BLK_NAME_LEN, "te2_%u",

					pp->id);

			set_bit(SDE_PINGPONG_TE2, &pp->features);

			set_bit(SDE_PINGPONG_SPLIT, &pp->features);

		}
@@ -1822,6 +1871,8 @@ static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg) 
		sblk->dsc.base = PROP_VALUE_ACCESS(prop_value, DSC_OFF, i);

		if (sblk->dsc.base) {

			sblk->dsc.id = SDE_PINGPONG_DSC;

			snprintf(sblk->dsc.name, SDE_HW_BLK_NAME_LEN, "dsc_%u",

					pp->id);

			set_bit(SDE_PINGPONG_DSC, &pp->features);

		}

	}
@@ -1864,9 +1915,13 @@ static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
	cfg->mdss_count = 1;

	cfg->mdss[0].base = MDSS_BASE_OFFSET;

	cfg->mdss[0].id = MDP_TOP;

	snprintf(cfg->mdss[0].name, SDE_HW_BLK_NAME_LEN, "mdss_%u",

			cfg->mdss[0].id);



	cfg->mdp_count = 1;

	cfg->mdp[0].id = MDP_TOP;

	snprintf(cfg->mdp[0].name, SDE_HW_BLK_NAME_LEN, "top_%u",

		cfg->mdp[0].id);

	cfg->mdp[0].base = PROP_VALUE_ACCESS(prop_value, SDE_OFF, 0);

	cfg->mdp[0].len = PROP_VALUE_ACCESS(prop_value, SDE_LEN, 0);

	if (!prop_exists[SDE_LEN])

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+6 −0
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ 


#define IS_SDM845_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_400)



#define SDE_HW_BLK_NAME_LEN	16



#define MAX_IMG_WIDTH 0x3fff

#define MAX_IMG_HEIGHT 0x3fff
@@ -241,12 +243,14 @@ enum { 


/**

 * MACRO SDE_HW_BLK_INFO - information of HW blocks inside SDE

 * @name:              string name for debug purposes

 * @id:                enum identifying this block

 * @base:              register base offset to mdss

 * @len:               length of hardware block

 * @features           bit mask identifying sub-blocks/features

 */

#define SDE_HW_BLK_INFO \

	char name[SDE_HW_BLK_NAME_LEN]; \

	u32 id; \

	u32 base; \

	u32 len; \
@@ -254,12 +258,14 @@ enum { 


/**

 * MACRO SDE_HW_SUBBLK_INFO - information of HW sub-block inside SDE

 * @name:              string name for debug purposes

 * @id:                enum identifying this sub-block

 * @base:              offset of this sub-block relative to the block

 *                     offset

 * @len                register block length of this sub-block

 */

#define SDE_HW_SUBBLK_INFO \

	char name[SDE_HW_BLK_NAME_LEN]; \

	u32 id; \

	u32 base; \

	u32 len

drivers/gpu/drm/msm/sde/sde_hw_cdm.c

+1 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ static struct sde_cdm_cfg *_cdm_offset(enum sde_cdm cdm, 
		if (cdm == m->cdm[i].id) {

			b->base_off = addr;

			b->blk_off = m->cdm[i].base;

			b->length = m->cdm[i].len;

			b->hwversion = m->hwversion;

			b->log_mask = SDE_DBG_MASK_CDM;

			return &m->cdm[i];

drivers/gpu/drm/msm/sde/sde_hw_ctl.c

+1 −0
Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ static struct sde_ctl_cfg *_ctl_offset(enum sde_ctl ctl, 
		if (ctl == m->ctl[i].id) {

			b->base_off = addr;

			b->blk_off = m->ctl[i].base;

			b->length = m->ctl[i].len;

			b->hwversion = m->hwversion;

			b->log_mask = SDE_DBG_MASK_CTL;

			return &m->ctl[i];