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Commit a3370850 authored by muluhe's avatar muluhe
Browse files

ARM: dts: msm: add swao csr node 



Add one more swao csr node for timestamp, the CSR driver supports multi
configuration.

Change-Id: I428319c9b953bc9903cdc71900c0d9eac267b572
Signed-off-by: default avatarmuluhe <muluhe@codeaurora.org>
parent 71721a67

arch/arm64/boot/dts/qcom/sdm845-coresight.dtsi

+22 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -18,6 +18,23 @@ 
		reg-names = "csr-base";



		coresight-name = "coresight-csr";

		qcom,usb-bam-support;

		qcom,hwctrl-set-support;

		qcom,set-byte-cntr-support;



		qcom,blk-size = <1>;

	};



	swao_csr: csr@6b0e000 {

		compatible = "qcom,coresight-csr";

		reg = <0x6b0e000 0x1000>;

		reg-names = "csr-base";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";



		coresight-name = "coresight-swao-csr";

		qcom,timestamp-support;



		qcom,blk-size = <1>;

	};
@@ -113,6 +130,7 @@ 
		reg-names = "tmc-base";



		coresight-name = "coresight-tmc-etf-swao";

		coresight-csr = <&csr>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -277,6 +295,7 @@ 


		coresight-name = "coresight-tmc-etr";

		coresight-ctis = <&cti0 &cti8>;

		coresight-csr = <&csr>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";
@@ -301,6 +320,7 @@ 


		coresight-name = "coresight-tmc-etf";

		coresight-ctis = <&cti0 &cti8>;

		coresight-csr = <&csr>;

		arm,default-sink;



		clocks = <&clock_aop QDSS_CLK>;
@@ -405,6 +425,7 @@ 
			    "ddr-ch23-ctrl";



		coresight-name = "coresight-hwevent";

		coresight-csr = <&csr>;



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";