Loading drivers/gpu/msm/adreno.h +9 −7 Original line number Diff line number Diff line Loading @@ -1926,6 +1926,7 @@ static inline int adreno_vbif_clear_pending_transactions( * Need to release CX Halt explicitly in case of SW_RESET. * GX Halt release will be taken care by SW_RESET internally. */ if (gpudev->gx_is_on(adreno_dev)) { adreno_writereg(adreno_dev, ADRENO_REG_RBBM_GPR0_CNTL, GBIF_HALT_REQUEST); ret = adreno_wait_for_vbif_halt_ack(device, Loading @@ -1933,6 +1934,7 @@ static inline int adreno_vbif_clear_pending_transactions( VBIF_RESET_ACK_MASK); if (ret) return ret; } adreno_writereg(adreno_dev, ADRENO_REG_GBIF_HALT, mask); ret = adreno_wait_for_vbif_halt_ack(device, Loading Loading
drivers/gpu/msm/adreno.h +9 −7 Original line number Diff line number Diff line Loading @@ -1926,6 +1926,7 @@ static inline int adreno_vbif_clear_pending_transactions( * Need to release CX Halt explicitly in case of SW_RESET. * GX Halt release will be taken care by SW_RESET internally. */ if (gpudev->gx_is_on(adreno_dev)) { adreno_writereg(adreno_dev, ADRENO_REG_RBBM_GPR0_CNTL, GBIF_HALT_REQUEST); ret = adreno_wait_for_vbif_halt_ack(device, Loading @@ -1933,6 +1934,7 @@ static inline int adreno_vbif_clear_pending_transactions( VBIF_RESET_ACK_MASK); if (ret) return ret; } adreno_writereg(adreno_dev, ADRENO_REG_GBIF_HALT, mask); ret = adreno_wait_for_vbif_halt_ack(device, Loading