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Commit a0d3c7c5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma 

Pull dmaengine updates from Vinod Koul:
 "This time round the update brings in following changes:

   - new tegra driver for ADMA device

   - support for Xilinx AXI Direct Memory Access Engine and Xilinx AXI
     Central Direct Memory Access Engine and few updates to this driver

   - new cyclic capability to sun6i and few updates

   - slave-sg support in bcm2835

   - updates to many drivers like designware, hsu, mv_xor, pxa, edma,
     qcom_hidma & bam"

* tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (84 commits)
  dmaengine: ioatdma: disable relaxed ordering for ioatdma
  dmaengine: of_dma: approximate an average distribution
  dmaengine: core: Use IS_ENABLED() instead of checking for built-in or module
  dmaengine: edma: Re-evaluate errors when ccerr is triggered w/o error event
  dmaengine: qcom_hidma: add support for object hierarchy
  dmaengine: qcom_hidma: add debugfs hooks
  dmaengine: qcom_hidma: implement lower level hardware interface
  dmaengine: vdma: Add clock support
  Documentation: DT: vdma: Add clock support for dmas
  dmaengine: vdma: Add config structure to differentiate dmas
  MAINTAINERS: Update Tegra DMA maintainers
  dmaengine: tegra-adma: Add support for Tegra210 ADMA
  Documentation: DT: Add binding documentation for NVIDIA ADMA
  dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access Engine
  Documentation: DT: vdma: update binding doc for AXI CDMA
  dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine
  Documentation: DT: vdma: update binding doc for AXI DMA
  dmaengine: vdma: Rename xilinx_vdma_ prefix to xilinx_dma
  dmaengine: slave means at least one of DMA_SLAVE, DMA_CYCLIC
  dmaengine: mv_xor: Allow selecting mv_xor for mvebu only compatible SoC
  ...
parents ec67b14c f9114a54

Documentation/ABI/testing/sysfs-platform-hidma

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+9 −0
Original line number Diff line number Diff line 
What:		/sys/devices/platform/hidma-*/chid

		/sys/devices/platform/QCOM8061:*/chid

Date:		Dec 2015

KernelVersion:	4.4

Contact:	"Sinan Kaya <okaya@cudeaurora.org>"

Description:

		Contains the ID of the channel within the HIDMA instance.

		It is used to associate a given HIDMA channel with the

		priority and weight calls in the management interface.

Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt

+26 −0
Original line number Diff line number Diff line
@@ -12,6 +12,10 @@ Required properties: 
- reg: Should contain DMA registers location and length.

- interrupts: Should contain the DMA interrupts associated

		to the DMA channels in ascending order.

- interrupt-names: Should contain the names of the interrupt

		   in the form "dmaXX".

		   Use "dma-shared-all" for the common interrupt line

		   that is shared by all dma channels.

- #dma-cells: Must be <1>, the cell in the dmas property of the

		client device represents the DREQ number.

- brcm,dma-channel-mask: Bit mask representing the channels
@@ -34,13 +38,35 @@ dma: dma@7e007000 { 
		     <1 24>,

		     <1 25>,

		     <1 26>,

		     /* dma channel 11-14 share one irq */

		     <1 27>,

		     <1 27>,

		     <1 27>,

		     <1 27>,

		     /* unused shared irq for all channels */

		     <1 28>;

	interrupt-names = "dma0",

			  "dma1",

			  "dma2",

			  "dma3",

			  "dma4",

			  "dma5",

			  "dma6",

			  "dma7",

			  "dma8",

			  "dma9",

			  "dma10",

			  "dma11",

			  "dma12",

			  "dma13",

			  "dma14",

			  "dma-shared-all";



	#dma-cells = <1>;

	brcm,dma-channel-mask = <0x7f35>;

};





DMA clients connected to the BCM2835 DMA controller must use the format

described in the dma.txt file, using a two-cell specifier for each channel.

Documentation/devicetree/bindings/dma/mv-xor.txt

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* Marvell XOR engines



Required properties:

- compatible: Should be "marvell,orion-xor" or "marvell,armada-380-xor"

- compatible: Should be one of the following:

  - "marvell,orion-xor"

  - "marvell,armada-380-xor"

  - "marvell,armada-3700-xor".

- reg: Should contain registers location and length (two sets)

    the first set is the low registers, the second set the high

    registers for the XOR engine.

Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.txt

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* NVIDIA Tegra Audio DMA (ADMA) controller



The Tegra Audio DMA controller that is used for transferring data

between system memory and the Audio Processing Engine (APE).



Required properties:

- compatible: Must be "nvidia,tegra210-adma".

- reg: Should contain DMA registers location and length. This should be

  a single entry that includes all of the per-channel registers in one

  contiguous bank.

- interrupt-parent: Phandle to the interrupt parent controller.

- interrupts: Should contain all of the per-channel DMA interrupts in

  ascending order with respect to the DMA channel index.

- clocks: Must contain one entry for the ADMA module clock

  (TEGRA210_CLK_D_AUDIO).

- clock-names: Must contain the name "d_audio" for the corresponding

  'clocks' entry.

- #dma-cells : Must be 1. The first cell denotes the receive/transmit

  request number and should be between 1 and the maximum number of

  requests supported. This value corresponds to the RX/TX_REQUEST_SELECT

  fields in the ADMA_CHn_CTRL register.





Example:



adma: dma@702e2000 {

	compatible = "nvidia,tegra210-adma";

	reg = <0x0 0x702e2000 0x0 0x2000>;

	interrupt-parent = <&tegra_agic>;

	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,

		     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

	clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;

	clock-names = "d_audio";

	#dma-cells = <1>;

};

Documentation/devicetree/bindings/dma/qcom_bam_dma.txt

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Original line number Diff line number Diff line
@@ -13,6 +13,8 @@ Required properties: 
- clock-names: must contain "bam_clk" entry

- qcom,ee : indicates the active Execution Environment identifier (0-7) used in

  the secure world.

- qcom,controlled-remotely : optional, indicates that the bam is controlled by

  remote proccessor i.e. execution environment.



Example: