clk: msm: Fixup for cpu clock driver for SDM632

CPU clock driver for SDM632 needs few fixes which
are identified during testing it on actual hardware.
This patch fixes the following:
- Skip odd divider for CCI mux.
- Correct offset for CCI PLL.
- Support to populate OPP table.
- Add dummy p_clk to set rate on CCI PLL in early init.
- Change name of PWR, PERF and CCI clocks.

Change-Id: Ia47b56776713c019152c044191f5ce71e4b88296
Signed-off-by: Amit Nischal <anischal@codeaurora.org>