Merge "clk: Account for rate differences due to PLL fractional programming" into msm-4.9 (9c2b6347) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/clk/clk.c

+7 −1

Original line number	Diff line number	Diff line
		@@ -1709,8 +1709,14 @@ static struct clk_core clk_calc_new_rates(struct clk_core core,
		}
		}

		/*
		* The Fabia PLLs only have 16 bits to program the fractional divider.
		* Hence the programmed rate might be slightly different than the
		* requested one.
		*/
		if ((core->flags & CLK_SET_RATE_PARENT) && parent &&
		best_parent_rate != parent->rate)
		(DIV_ROUND_CLOSEST(best_parent_rate, 1000) !=
		DIV_ROUND_CLOSEST(parent->rate, 1000)))
		top = clk_calc_new_rates(parent, best_parent_rate);

		out: